Intel Corporation

Jinhong Shin

Christopher P Auth

Joseph M Steigerwald

Andrew W Yeoh

Vinay B Chikarmane

Atul Madhavan

Anant H Jahagirdar

Abhishek Jain

Vinay Chikarmane

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication. In an example, an integrated circuit structure includes a single dielectric layer above a substrate. A plurality of conductive lines is in an upper portion of the single dielectric layer above a lower portion of the single dielectric layer. A carbon dopant region is in the upper portion of the single dielectric layer, the carbon dopant region between adjacent ones of the plurality of conductive lines.

Dielectric capacitance recovery of inter-layer dielectric layers for advanced integrated circuit structure fabrication

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Heterogeneous metal line compositions for advanced integrated circuit structure fabrication

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Hillsboro, OR, United States of America

Jinhong Shin