Oracle International Corporation

Jinho Kwack

Hoyeol Cho

Jungyong Lee

Heechoul Park

Ioannis Orginos

Myung Gyoo Won

Joann Lam

Peter Normand Labrecque

Tsunghsun Hsieh

Claire Ni

Jilong Shan

Embodiments include systems and methods for improving column selection functionality of memory circuits. Embodiments operate in context of memory bitcells having additional series pass gates (e.g., junction sharing transistors) coupled with a column select signal to form an integrated column select port. Such a column select port can provide each bitcell with column select functionality in a manner that has improved area and power performance over some conventional (added NOR or other logic) approaches. However, the added column select port can still tend to add area, add column select load, and degrade writability (e.g., due to certain charge-sharing effects). Some embodiments are described herein for addressing the area and column select load by sharing certain intermediate nodes among multiple, adjacent bitcells. Other embodiments can include additional ground-connected transistors in a manner that improves writability (e.g., and read noise margin) of the bitcell.

Memory bitcell with column select

Embodiments include systems and methods for providing robust clock-skew-tolerant memory updating in high-speed memory circuits. For example, in each memory update interval, update of a pre-memory with un-validated update data begins when a potential match is detected between a tag memory and a key (whether according to a base clock or a delayed clock); but the update data is not considered valid (nor is it written out as such) until a determination is made according to the delayed clock. The un-validated update data can be written out from the pre-memory as validated update data for the memory update interval upon detection of a data valid indication generated from the delayed hit indication.

Clock-skew-tolerant memory updating

Embodiments include systems and methods for improving power consumption characteristics of reverse directories in microprocessors. Some embodiments operate in context of multiprocessor semiconductors having cache hierarchies in which multiple higher-level caches share lower-level caches. Lower-level cache is coupled with reverse directories associated with respective ones of the higher-level caches. Each reverse directory can be segregated into two reverse sub-directories, one reverse sub-directory for relatively high-frequency accesses (e.g., updating 'valid' and/or 'private' information), and the other reverse sub-directories for relatively low-frequency accesses updating &#x201c;index&#x201d; and &#x201c;way&#x201d; information). During a write mode operation, when the reverse directories are updated, the write operation is performed only on the sub-directories having the entries invoked by the update, such that write operations can frequently consume only a fraction (e.g., halt) of the power of a conventional reverse directory write operation.

Power saving for reverse directory

Systems, methods, and other embodiments associated with conserving power using variable width pulses to activate word lines are described. In one embodiment, a memory device embedded within a processor. The memory device includes a pulse shaper to generate a first timing delay and a second timing delay according to power state information. The power state information indicates a current operating state of the processor. The memory device includes a memory controller to generate, in response to receiving a request to access one or more memory cells of the memory device, a word line enable signal that activates the one or more memory cells according to the first timing delay, the second timing delay, and a clock signal by generating the word line enable signal with a pulse width that is variable to conserve power when the state information indicates the processor is in a power saving state.

Variable pulse widths for word line activation using power state information

Systems, methods, and other embodiments associated with speculating whether a read request will cause an access to a memory are described. In one embodiment, a method includes detecting, in a memory, a read request from a processor and speculating whether the read request will cause an access to a memory bank in the memory based, at least in part, on an address identified by the read request. The method selectively enables power to the memory bank in the memory based, at least in part, on speculating whether the read request will cause an access to the memory bank.

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Santa Clara, CA, United States of America

Jinho Kwack