Advanced Semiconductor Engineering, Inc.

JinHee Won

Sangbae Park

Junyoung Yang

Hyeongno Kim

HyungJun Park

YongGil Lee

KyungSoo Rho

A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is etched away to form a first connection pad and a second connection pad which are separated from each other but are still electrically connected to each other via the first metal layer therebetween. Then, a second metal layer is electroplated on the connection pads and the die pads by using the first metal layer as an electrical path. Finally, the first metal layer between the first connection pads and the second connection pads is removed, and a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.

Process and lead frame for making leadless semiconductor packages

A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. Each lead of the lead frame has a first portion, a second portion and a third portion connecting the first portion and the second portion, wherein the first metal layer is not provided on the third portion. After a wire bonding step and an encapsulating step are conducted, a second metal layer is selectively plated on the first portions and the second portions of the leads and the die pads exposed from the bottom of the molded product. Then, the third portion of each lead is selectively etched away such that the first portion and the second portion are electrically isolated from each other. Finally, a singulation step is conducted to complete the process. The present invention further provides a new lead frame design.

Growing community of inventors

Paju-si, South Korea

JinHee Won