Lg Display Co., Ltd.

Jinhee Jung

MooKyoung Hong

Two or more sensing switches are included in a sensing unit for detecting a characteristic value of a subpixel, and are electrically coupled to a reference voltage line. The two or more sensing switches share a sampling switch with a sensing capacitor included in the sensing unit, which reduces size of the sensing unit. Sensing may include driving simultaneously two or more sensing switches sharing a sensing capacitor, or sensing may be performed through continuous and short driving after simultaneous driving. Overall sensing time can be reduced and sensing accuracy improved.

Data driving circuit and display device

A display device and a driving circuit are discussed. According to an embodiment of the present disclosure, it is possible to stably maintain the output signal of the driving circuit when the lock signal indicating the synchronization state of the clock signal is changed due to an operation error such as overcurrent in a display device using a point-to-point interface. In addition, according to an embodiment of the present disclosure, it is possible to prevent damage to the display panel due to an overload generated in the output signal of the driving circuit by an operation error. In addition, according to an embodiment of the present disclosure, it is possible to prevent overload of the driving circuit and damage to the display panel by controlling the operation of the driving circuit through a differential input voltage between the timing controller and the driving circuit.

Display device and driving circuit having improved stability

A display device may include: a display panel including a plurality of sub pixels; a data driving circuit configured to supply image data or fake data to a plurality of data lines; and a gate driving circuit configured to supply gate signals to a plurality of gate lines. The data driving circuit may supply the fake data to the plurality of data lines before the gate signal for an (n+1)th gate line is supplied after the gate signal for an n-th gate line is supplied, and a turn-on level period of the gate signal for the n-th gate line may include an overlap period that overlaps a turn-on level period of the gate signal for an (n&#x2212;1)th gate line and a non-overlap period that does not overlap the turn-on level period of the gate signal for the (n&#x2212;1)th gate line.

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Samcheok-si, South Korea

Jinhee Jung