Applied Materials, Inc.

Texas Instruments Corporation

Jinhan Choi

Brian Keith Kirkpatrick

Anisul Haque Khan

Shashank C Deshmukh

Byungkook Kong

Hun Sang Kim

Kyeong-Tae Lee

Hoon Sang Lee

Xiaosong Ji

Jinsu Kim

Ho Jeong Kim

Thorsten B Lill

Freidoon Mehrad

Minoru Takahashi

Meihua Shen

Frank Scott Johnson

Olivier Luere

Sunil Srinivasan

Deborah J Riley

Kang-Lie Chiang

Rohit Mishra

Xiawan Yang

Sang In Yi

Shinichi Koseki

Bi Jang

Randall W Pak

Wei Wu

Yongjia Li

Mir Abdulla Al Galib

Masato Ito

Jae Bum Yu

Feng Zhang

Disclosed herein is a high throughput method for providing directional protection to a three dimensional feature on a substrate by forming a multi-layer amorphous carbon-containing coating with tunable conformality thereon. Forming the multi-layer amorphous carbon-containing coating with tunable conformality includes depositing a base layer onto a horizontal surface of the three dimensional features, and a second layer over the base layer and onto a first portion of a vertical or inclined surface of the three dimensional feature. The base layer includes a first material with a first sticking coefficient and the second layer includes a second material with a second sticking coefficient that is smaller than the first sticking coefficient. The first material includes no fluorine or less fluorine than the second material. Also disclosed herein is a method of manufacturing a three dimensional device as well as three dimensional devices.

Amorphous carbon multilayer coating with directional protection

In an embodiment, a method of processing a substrate includes introducing a first process gas or a mixture of the first process gas and a second process gas into an etch chamber; exposing the substrate to the first process gas or to the mixture of the first and second process gases, the substrate having halogen residue formed on an exposed surface, the substrate having high aspect ratio features; forming and maintaining a plasma of the first process gas or a plasma of the mixture of the first and second process gases in the etch chamber to remove the residue from the surface by applying a first source power; exposing the substrate to the second process gas; and forming and maintaining a plasma of the second process gas in the etch chamber to remove the residue from the surface by applying a second source power and a bias power.

Halogen abatement for high aspect ratio channel device damage layer removal for EPI growth

Embodiments of methods for forming features in a silicon containing layer of a substrate disposed on a substrate support are provided herein. In some embodiments, a method for forming features in a silicon containing layer of a substrate disposed on a substrate support in a processing volume of a process chamber includes: exposing the substrate to a first plasma formed from a first process gas while providing a bias power to the substrate support, wherein the first process gas comprises one or more of a chlorine-containing gas or a bromine containing gas; and exposing the substrate to a second plasma formed from a second process gas while no bias power is provided to the substrate support, wherein the second process gas comprises one or more of an oxygen-containing gas or nitrogen gas, and wherein a source power provided to form the first plasma and the second plasma is continuously provided.

Method for forming features in a silicon containing layer

Methods of patterning a blanket layer (a target etch layer) on a substrate are described. The methods involve multiple patterning steps of a mask layer several layers above the target etch layer. The compound pattern, made from multiple patterning steps, is later transferred in one set of operations through the stack to save process steps.

Simplified litho-etch-litho-etch process

Local and global reduction of critical dimension (CD) asymmetry in etch processing is described. In an example, a method of etching a wafer of to form a plurality of staircase structures with reduced local and global asymmetry involves forming a photoresist layer on a plurality of micron-scale semiconductor structures. The photoresist layer is then trimmed with a high pressure and pulsed plasma etch process performed in a reverse MESA mode.

Local and global reduction of critical dimension (CD) asymmetry in etch processing

Embodiments of methods for etching a substrate include exposing the substrate to a first plasma formed from an inert gas; exposing the substrate to a second plasma formed from an oxygen-containing gas to form an oxide layer on a bottom and sides of a low aspect ratio feature and a high aspect ratio feature, wherein the oxide layer on the bottom of the low aspect ratio feature is thicker than on the bottom of the high aspect ratio feature; etching the oxide layer from the bottom of the low and high aspect ratio features with a third plasma to expose the bottom of the high aspect ratio feature while the bottom of the low aspect ratio feature remains covered; and exposing the substrate to a fourth plasma formed from a halogen-containing gas to etch the bottom of the low aspect ratio feature and the high aspect ratio feature.

Aspect ratio dependent etch (ARDE) lag reduction process by selective oxidation with inert gas sputtering

A method and apparatus for plasma etching a workpiece, such as a semiconductor wafer, including a thin film stack having a top film disposed over a bottom film with an intervening middle film there between. Etch selectivity between the top and bottom films may be as low as between 1:1 and 2:1 and a first carbon-lean gas chemistry is used to etch through the top film, a second carbon-lean gas chemistry is used to etch through the middle film, and the bottom film is etched through by alternating between depositing a polymer passivation on the top film using a carbon-rich gas chemistry and an etching of the bottom film with a third carbon-lean gas chemistry, which may be the same as the first carbon-lean gas chemistry.

Multi-film stack etching with polymer passivation of an overlying etched layer

A method of forming an integrated circuit having an NMOS transistor and a PMOS transistor is disclosed. The method includes performing pre-gate processing in a NMOS region and a PMOS region over and/or in a semiconductor body, and depositing a polysilicon layer over the semiconductor body in both the NMOS and PMOS regions. The method further includes performing a first type implant into the polysilicon layer in one of the NMOS region and PMOS region, and performing an amorphizing implant into the polysilicon layer in both the NMOS and PMOS regions, thereby converting the polysilicon layer into an amorphous silicon layer. The method further includes patterning the amorphous silicon layer to form gate electrodes, wherein a gate electrode resides in both the NMOS and PMOS regions.

Reducing gate CD bias in CMOS processing

A method for fabricating a CMOS integrated circuit (IC) includes providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the semiconductor surface followed by forming at least a first metal including layer on the gate dielectric layer. A polysilicon or amorphous silicon layer is formed on the first metal including layer to form an intermediate gate electrode stack. A masking pattern is formed on the intermediate gate electrode stack. The polysilicon or amorphous silicon layer is dry etched using the masking pattern to define a patterned intermediate gate electrode stack over the NMOS or PMOS regions, wherein the dry etching stops on a portion of the first metal comprising layer. The masking pattern is removed using a first post etch clean for stripping the masking pattern. A multi-step solution cleaning sequence is used after the removing step and includes a first wet clean including sulfuric acid and a fluoride, and a second wet clean after the first wet clean including a fluoride. Fabrication of the IC is then completed.

Post metal gate VT adjust etch clean

A method of plasma etching tungsten silicide over polysilicon particularly useful in fabricating flash memory having both a densely packed area and an open (iso) area requiring a long over etch due to microloading. Wafer biasing is decreased in the over etch. The principal etchant include NFand Cl. Argon is added to prevent undercutting at the dense/iso interface. Oxygen and nitrogen oxidize any exposed silicon to increase etch selectivity and straightens the etch profile. SiClmay be added for additional selectivity.

Process for etching tungsten silicide overlying polysilicon particularly in a flash memory

A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.

Post high-k dielectric/metal gate clean

A method of etching metals and/or metal-containing compounds using a plasma comprising a bromine-containing gas. In one embodiment, the method is used during fabrication of a gate structure of a field effect transistor having a titanium nitride gate electrode, an ultra-thin (about 10 to 20 Angstroms) silicon dioxide gate dielectric, and a polysilicon upper contact. In a further embodiment, the gate electrode is selectively notched to a pre-determined width.

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San Ramon, CA, United States of America

Jinhan Choi