Huawei Technologies Co., Limited

Jingzhou Yu

Linchun Wang

Yang Liu

Cong Liu

Xiaojun Zhang

Xiang Yu

Xiaofei Xu

Hui Lu

Qingzhi Liu

Liwei Zhou

Lingbo Guo

Yusheng Xing

Zijian He

Xingtao Yan

Wenzong Yang

A data search apparatus includes a logical search circuit and a memory, and the logical search circuit is connected to the memory through a databus. The databus can access all memory resources, and each part of databus resource can access all the memory resources. A logical search resource provided by the logical search circuit can be divided into a plurality of parts as required, and each part of logical resource can access node data in the memory through the bus resource.

Data search method and apparatus, and integrated circuit

This application provides for data transmission between first and second network devices. The first network device requests information from the second network device and in return receives grant information from the second network device. The grant information includes at least a first sequence number that is used by the first network device to determine a first credit limit, where the first credit limit is an amount of data allowed to be sent by the first network device in a packet-distributed load sharing manner. The first network device sends data to the second network device based on the first credit limit. Second and third sequence numbers are also described.

Data transmission method and network device

This application relates to the field of storage technologies and discloses a content addressable memory, a data processing method, and a network device, to resolve a problem that an existing CAM has a relatively large area, and consumes relatively large power. The CAM includes bit units of M rows and N columns, each bit unit includes a first FeFET and a second FeFET, a source of the first FeFET is connected to a drain of the second FeFET, a source of the second FeFET is grounded, bit cells of a same column correspond to a same match line, and a drain of a first FeFET in each bit cell of a same column is connected to a match line corresponding to the column. Bit cells of a same row correspond to a same first bit line and a same second bit line, a gate of a first FeFET in each bit cell of a same row is connected to a first bit line corresponding to the row, and a gate of a second FeFET in each bit cell of a same row is connected to a second bit line corresponding to the row. The CAM may be applied to a network device such as a router.

Content addressable memory, data processing method, and network device

A packet processing method and apparatus relating to the field of communications technologies are provided, so as to reduce overheads and improve update efficiency. The method includes: receiving a first packet and a second packet; determining a first instruction block; obtaining a first identifier according to the first instruction block and the first packet, and obtaining a second identifier according to the first instruction block and the second packet, the first entry includes a third identifier, and the third identifier is a storage address of a second instruction block; obtaining the third identifier by accessing the first entry indicated by the first identifier, and obtaining the third identifier by accessing the first entry indicated by the second identifier; obtaining the second instruction block according to the third identifier; and processing the first packet and the second packet according to the second instruction block.

Packet processing method and apparatus

Embodiments of the present disclosure disclose a route search method and apparatus, and a routing device. The method includes: obtaining a keyword; obtaining node data based on a pre-obtained storage address of the node data; determining, in the node data, data corresponding to the keyword; when the data is a storage address of next-level node data and a storage location of the next-level node data, obtaining a storage location of the node data; when the storage location of the node data is different from the storage location of the next-level node data, adding a search identifier, the storage address of the next-level node data, and a remaining part of the keyword to a frame header of a packet; and sending the packet having the frame header to a specified board corresponding to the storage location of the next-level node data.

Route search method and apparatus, and routing device

The present disclosure relates to registration methods and devices. One example method includes obtaining, by a line card, line card information of the line card, the line card comprising a fabric interface chip optically interconnected to a switch fabric chip in at least one switch fabric card by using an optical fiber, and sending, by the line card, the line card information to the at least one switch fabric card through an optical interconnect path. The at least one switch fabric card registers the line card based on the line card information.

Board registration method, board, and forwarding device

A route searching method and apparatus, an allocation node, a searching node, and an ingress node are provided. The method includes: receiving, by an allocation node, a destination IP address of a packet sent by an ingress node, where an allocation table on the allocation node includes a match item field and a searching node number field; performing, by the allocation node, matching of the match item field in the allocation table according to the destination IP address in an LPM principle; if the destination IP address successfully matches a first match item field in the allocation table, obtaining, by the allocation node, a physical box number of a first searching node on which routing information of a first prefix subtree corresponding to the first match item field is located; and sending, by the allocation node, the destination IP address to the first searching node.

Growing community of inventors

Beijing, China

Jingzhou Yu