Xilinx, Inc.

Jingzhao Ou

Chi Bun Chan

Shay Ping Seng

Haibing Ma

Nabeel Shirazi

Jeffrey Stroomer

Arvind Sundararajan

Roger Brent Milne

A computer implemented method for designing a circuit includes associating a high level design constraint with a first high level circuit component of a high level circuit design within a high level modeling system and translating the high level circuit design into a low level circuit design comprising at least one low level circuit component derived from the first high level circuit component. The method also includes automatically generating at least one low level design constraint from the high level design constraint for at least one low level circuit component and storing each low level design constraint in association with the low level circuit design.

Using constraints wtihin a high-level modeling system for circuit design

Within a system comprising a processor and a memory, a method of automatically documenting a circuit design can include determining an assignment of a user comment entity (UCE) of a high level modeling system (HLMS) circuit design to an HLMS block of the HLMS circuit design, translating each HLMS block of the HLMS circuit design into a hardware description language (HDL) representation of the HLMS block, and for each HLMS block assigned a UCE, inserting within the HDL representation, by the processor, content of the UCE that is assigned to the HLMS block in the form of a comment. The HDL representations can be stored within the memory.

Automatically documenting circuit designs

Approaches for simulating a circuit design. A block diagram of the circuit design is displayed. Each block has at least one input and at least one output, and at least one of the input or output of each block is connected to another block. Simulation data are input to a simulation model of the circuit design. During simulation of each of a plurality of the sub-circuits with the simulation model, an output data value is determined from one or more input data values to the simulated sub-circuit. Concurrent with determining the output data value, an output tag value corresponding to the output data value is determined. Concurrent with output of the output data value from the simulated sub-circuit, each output tag value is displayed proximate an output signal line from the block corresponding to the sub-circuit.

Signal tagging during simulation

A method of performing a simulation of a design under test is disclosed. The method comprises implementing an input block having an adjustable output width; coupling test data to the input block; generating an input signal comprising the test data for the design under test according to an input requirement for the design under test by way of the input block; implementing an output block having an adjustable input width for receiving data from an output of the design under test; and coupling the output of the design under test to the output block according to an output requirement of the design under test. A circuit for enabling testing of a circuit design implemented in an integrated circuit is also disclosed.

Method of performing a simulation of a design under test and a circuit for enabling testing of a circuit design

Various approaches for co-simulating an electronic system design are described. In one approach, a hardware design function block in the design is instantiated, along with a specification of a software execution platform including external ports and software to execute on the platform. In response to a user instruction to import the software execution platform into the design, a software execution platform interface block is automatically instantiated. A first simulation model is generated from the hardware design function block and the software execution platform interface block and a second simulation model is generated from the software execution platform. The design is co-simulated using the first and second simulation models. Data is communicated between the first simulation model and the second simulation model via the interface block.

System-level hardware and software development and co-simulation system

Disclosed are approaches for operating a plurality of debugger tools. A common debugger receives first-type commands for processing. Each first-type command references one of the debugger tools. Each debugger tool provides control over a respective set of one or more components of the electronic system and recognizes a respective set of tool-specific commands. Each input first-type command is translated into a respective tool-specific command that is compatible with the one of the debugger tools specified in the first-type command. Each respective tool-specific command from the common debugger is provided to the one of the debugger tools specified in the input first-type command from which the respective tool-specific command was translated. Each translated tool-specific command is performed by the targeted debugger tool.

Common debugger method and system

An embodiment of a method for enabling a high level modeling system for implementing a circuit design in an integrated circuit device includes: receiving a high-level characterization of the circuit design; receiving a portable location constraint associated with elements of the circuit design; and generating, by a computer, a low-level characterization of the circuit design based upon the high-level characterization and the portable location constraint.

Enabling a high-level modeling system

A computer-implemented method of creating a simulation engine for simulating a circuit design can include receiving a source code contribution from a high level modeling system and receiving a simulation model specified in an interpretive language that specifies the circuit design. The source code contribution can be compiled together with the simulation model using a Just-In-Time compiler. A simulation engine, specified in native machine code, can be output as a single, integrated software component formed from the source code contribution and the simulation model.

Reloadable just-in-time compilation simulation engine for high level modeling systems

Within a high level modeling system (HLMS) comprising a processor and a memory, a method can include executing a system template comprising a plurality of modules of an electronic system, wherein each module represents a hardware component of the electronic system and is specified in the form of an extendable, higher order function, and extending, during runtime, a first module of the plurality of modules with a first extension by binding, via the processor, the first extension to the first module. The plurality of modules comprising the first extension to the first module can be stored within the memory.

High level system design using functional and object-oriented composition

A high-level integrated circuit ('IC') modeling system () includes a first co-simulator () modeling a first portion of an IC system and a second co-simulator () modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating conditions (). A co-simulation synchronization interface () is configured to automatically change at least one of the initial simulation operating conditions to a triggered operating condition () in response to a user-selected triggering signal.

Co-simulation synchronization interface for IC modeling

A configurable memory map interface coupled to a circuit element having input/output ports is disclosed. The configurable memory map interface comprises an input coupled to receive an address enabling reading from or writing to the circuit element; a memory storing enable signal parameters, the enable signal parameters controlling timing of enable signals for the reading from or the writing to the circuit element; and an enable signal generator generating the enable signals enabling the reading from or the writing to the circuit element based upon the enable signal parameters stored in the memory. A method of implementing a configurable memory map interface is also disclosed.

Configurable memory map interface and method of implementing a configurable memory map interface

Method and apparatus for modeling processor-based circuit models are described. Some examples relate to designing a circuit model having a processor system and custom logic. A bus adapter coupled to a bus of the processor system is generated. A shared memory interface between the custom logic and the bus adapter is generated. The shared memory interface includes a memory map for the processor system. A clock wrapper having a first clock input and a second clock input is generated. The first clock input drives the custom logic and first shared memory of the shared memory interface. The second clock input drives the processor system.

Method and apparatus for modeling processor-based circuit models

A system can include a bus proxy comprising a primary slave coupled to a processor via a bus. The bus proxy system can include a hardware co-simulation interface disposed within the programmable IC and coupled to the bus proxy. The hardware co-simulation interface can buffer simulation data from the bus proxy and the host processing system. The bus proxy can include a secondary slave executing with a host processing system that reads data from, and writes data to, the hardware co-simulation interface, and communicates with at least one high level modeling system (HLMS) block executing within the host processing system. The primary slave can exert a slave wait signal on the bus responsive to detecting a bus request from the processor specifying an address corresponding to the HLMS block within the host processing system.

Hardware co-simulation involving a processor disposed on a programmable integrated circuit

A method of detecting differences between high level block diagram models using text based analysis. Previous methods of determining differences between high level block diagram models derive differences through traversal of the block hierarchy which is complex and cannot compare differences between models created with third party design environments. The present invention increases interoperability and capabilities of existing circuit design environments, and achieves an advance in the art, by converting high level block diagram models to a user readable text-based format and performing a text-based differential analysis on the converted models to determine differences.

Detecting differences between high level block diagram models

Approaches for preparing simulation models of an electronic circuit are disclosed. The design is partitioned into first and second clusters. The design includes a source module in the first cluster connected to a destination module in the second cluster. The first cluster is compiled into a first model for a software-based co-simulation platform for simulating behavior of the source module using the first model. The first cluster and the second cluster of the design are compiled into a second model for a hardware-based co-simulation platform that includes a programmable logic circuit configurable for emulating behavior of the design using the second model. An interconnection block is generated and stored in the second model. The interconnection block is switchable between coupling of the destination module in the second model to the source module of the first model or to a source module of the second model.

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Sunnyvale, CA, United States of America

Jingzhao Ou