Sandisk Technologies Inc.

Jingwen Ouyang

Tz-Yi Liu

Yingchang Chen

Henry Zhang

Anurag Nigam

Yukeun Sim

Jayesh Pakhale

Greg Hilton

Apparatuses, systems, methods, and computer program products are disclosed for queuing storage operations. An integrated circuit memory element receives a storage operation command associated with a bank of storage locations of a memory element. An integrated circuit memory element queues a storage operation command for execution on a bank of storage locations by determining a storage location in a page register for data associated with the storage operation command. A storage location in a page register includes a subset of available storage locations in the page register. An integrated circuit memory element stores data associated with a storage operation command at a determined storage location in a page register.

Storage operation queue

Techniques and memory devices are provided in which bit line short circuits are detected and groups of bit lines are masked off. A process tests groups of bit lines which are connected to a sense circuit. A masking latch is provided to store test results for each group of bit lines. Once the testing of a group is completed, the test result is communicated to a controller. Moreover, the same masking latch can store and communicate test results for multiple groups of bit lines which are connected to a sense circuit. In a user mode, a masking latch stores masking data for each group of bit lines. In response to a power on reset, the masking data is loaded into the masking latches and remains there over multiple write and read operation, until a next power on reset occurs.

Memory with bit line short circuit detection and masking of groups of bad bit lines

Apparatuses, systems, and methods are disclosed for controlling a data path for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a memory core. A memory core includes an array of non-volatile memory cells and an internal data pipeline. A memory die includes a buffer that stores data associated with storage operations for a memory core. A memory die includes an internal controller that communicates with a memory core to initiate storage operations. An internal controller may delay initiating a storage operation in response to determining that an internal data pipeline and a buffer are both full.

Data path control for non-volatile memory

Apparatuses, systems, and methods are disclosed for controlling commands for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a command/address buffer, an on-die controller, and a plurality of non-volatile memory cores that share a data path. A core includes an array of non-volatile memory cells. A command/address buffer queues command and address information for a plurality of storage operations for one or more non-volatile memory cores. An on-die controller initiates a first unexecuted read operation and a first unexecuted write operation from a command/address buffer in parallel, in response to determining that core dependencies are satisfied for a read operation and a write operation.

Command control for multi-core non-volatile memory

Apparatuses, systems, methods, and computer program products are disclosed for data register copying for a non-volatile storage array. An apparatus may include an array of non-volatile storage cells. A set of write buffer data registers may be configured to store target data for a program operation for an array. Write buffer data registers may communicate target data to corresponding columns of an array. A set of shadow data registers may be configured to receive target data from peripheral circuitry for an array. A portion of target data received by a shadow data register may be copied to a corresponding write buffer data register while the shadow data register receives the portion of the target data.

Data register copying for non-volatile storage array operations

Apparatuses, systems, methods, and computer program products are disclosed for redundancy mapping. A controller is configured to determine that one or more defects affect a subset of a first group of cells and a subset of a second group of cells of a non-volatile memory medium. A non-volatile memory medium may include a plurality of groups of cells, and redundant groups of cells may be available for replacing defective groups of cells. A controller is configured to store a mapping between affected subsets of first and second groups of cells and a redundant group of cells for a non-volatile memory medium. A controller is configured to read data for a first group and/or second group of cells by referencing a mapping and using a redundant group of cells.

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Mountain View, CA, United States of America

Jingwen Ouyang