Micron Technology Incorporated

Jingwei Cheng

Cheng Zhang

Chunqiang Weng

Methods, systems, and devices for configurable memory die capacitance are described. A memory device may include a capacitive component, which may include one or more capacitors and associated switching components. The capacitive component may be coupled with an input/output (I/O) pad and an associated input buffer, and the one or more capacitors of the capacitive component may be selectively couplable with the I/O pad via the switching components. Switching components may be activated individually, in coordination, or not at all, such that one, multiple, or none of the capacitors may be coupled with the I/O pad. The capacitive component, I/O pad, and input buffer may be included in a same die of the memory device. In some cases, a configuration of the capacitive component may be based on signaling received from a host device.

Configurable memory die capacitance

Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.

Testing circuit for a memory device

Methods, systems, and devices for debug capabilities of a memory system with a pin are described. An apparatus may include a memory system that includes a plurality of pins of a first type that are configured to communicate information as part of operating the memory system and a pin of a second type. The apparatus may also include a circuit coupled with the memory system, the circuit including a resistor that is coupled with the pin of the second type. The memory system may include a controller that selects a value for the resistor and generates a code as part of a memory management operation to determine one or more operating conditions of the memory system based on selecting the value. The memory system controller may also determine an error associated with the code based on generating the code and the selected value of the resistor.

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Shanghai, China

Jingwei Cheng