China Flash Co., Ltd.

Huawei Technologies Co., Limited

Tencent Technology (shenzhen) Company Limited

Jingwei Chen

Hong Nie

Zhenyu Xu

Wa Ye

Zheng Wang

Jing Zang

Mengsha Zhou

Yu Gong

Yonghong Wang

Jiongchao Lin

Sicheng Huang

Cunjin Li

Cunliang Li

Liang Chen

Ruosheng Xu

Peiku Li

Rui Gong

Cui Hu

Shuo Lian

Juanpeng He

Shuangquan Wang

Embodiments of this application provide an image transmission method and apparatus. The method includes: converting a first high-resolution image into a first low-resolution image, where first resolution of the first high-resolution image is higher than second resolution of the first low-resolution image; encoding the first low-resolution image to obtain a first bitstream; obtaining a second high-resolution image, where third resolution of the second high-resolution image is higher than the second resolution, and the second high-resolution image includes high-frequency information of the first high-resolution image and excludes low-frequency information of the first high-resolution image; obtaining an image residual between the first high-resolution image and the second high-resolution image, where the image residual is used to reflect the low-frequency information of the first high-resolution image; encoding the image residual to obtain a second bitstream; and sending the first bitstream and the second bitstream.

Image transmission method and apparatus

A method for programming a memory. The method includes providing a memory structure with a floating gate, and grounding a source of the memory structure; applying voltages to a drain and a bulk, forming an electric field, generating electron-hole pairs, and generating primary electrons, wherein the voltage applied to the bulk is lower than the voltage applied to the drain; making holes accelerate downward under the action of the electric field and collide with the bulk in the memory structure within a predetermined time to generate secondary electrons; applying voltages to a gate and the bulk respectively, where the voltage applied to the bulk is lower than the voltage applied to the gate, to enable the secondary electrons to generate tertiary electrons under the action of an electric field in a vertical direction, and the tertiary electrons are injected into the floating gate to complete a programming operation.

Method for programming memory

The present disclosure relates to a method for programming flash memory, which includes: providing a flash memory structure having a floating gate, and floating a source of the flash memory structure; separately applying voltages to a drain and a substrate, to form an electric field, and generating electron-hole pairs, to generate primary electrons, where the voltage applied to the substrate is less than the voltage applied to the drain; accelerating holes downward under the action of the electric field to collide with the substrate in the flash memory structure within a preset time, to generate secondary electrons; and separately applying voltages to a gate and the substrate, where the voltage applied to the substrate is less than the voltage applied to the gate, and enabling the secondary electrons to generate tertiary electrons to inject the tertiary electrons into the floating gate, to complete a programming operation.

Method for programming flash memory

The present disclosure provides a method for programming charge trap flash memory, including: enabling a channel of a charge trap storage component, to form a transverse electric field between a source and a drain, to generate primary electrons flowing from the source to the drain; colliding, by the primary electrons after a preset time, with the drain to generate electron holes; applying voltages to the drain and a substrate, where the electron holes are accelerated downward by the action of the electric field to collide with the substrate, to generate secondary electrons; and applying voltages to a gate and the substrate, to form a vertical electric field, wherein the secondary electrons generate tertiary electrons under the action of the vertical electric field and the tertiary electrons are injected into an insulating storage medium layer of the charge trap storage component, to complete a programming operation.

Method for programming charge trap flash memory

The present disclosure relates to a method for programming a 3D NAND flash memory, which includes: S) providing a 3D flash memory array, and eliminating residual charges; S) strobing a bit line where an upper sub-storage module is located; S) applying a drain voltage to the drain of a to-be-programmed memory cell, and floating a source thereof; S) applying a programming voltage to the gate of the to-be-programmed memory cell, to complete programming; and S) after completing the programming of the upper sub-storage module, and when the upper sub-storage module keeps a programmed state, strobing a bit line where a lower sub-storage module is located, and repeating operation S) and operation S) to achieve programming of the lower sub-storage module. In the method for programming a 3D NAND flash memory according to the present disclosure, programming is completed based on tertiary electron collision.

Method for programming 3D NAND flash memory

The present disclosure relates to a method for programming a NAND flash memory, which includes: providing a NAND flash memory array, and initializing a to-be-programmed memory cell; applying a drain voltage to the drain of the to-be-programmed memory cell, and floating the source of the to-be-programmed memory cell; and applying a programming voltage to the gate of the to-be-programmed memory cell, and discharging the voltage at each end of the to-be-programmed memory cell after maintaining the voltage for a first time period, to complete programming; a difference between the voltage applied to the drain and the voltage applied to the substrate of the to-be-programmed memory cell being not less than 4 V, the first time period being not longer than 100 &#x3bc;s, and the programming voltage being not higher than 10 V.

Method for programming NAND flash memory

A method for programming a B4 flash memory includes: floating a source of a P-channel flash memory device; separately applying voltages to a gate, a drain, and a bulk of the P-channel flash memory device, and injecting holes into the bulk, so that electrons are gathered in the drain to form primary electrons; separately applying voltages to the drain and the bulk, so that an electric field is formed between the drain and the bulk, where the holes accelerate downward under the action of the electric field and impact the bulk in the P-channel flash memory device to generate secondary electrons; and separately applying voltages to the gate and the bulk of the P-channel flash memory device, so that the secondary electrons form tertiary electrons under the action of the electric field in a vertical direction, where the tertiary electrons are superposed with the primary electrons to be injected into a floating gate.

Method for programming B4 flash memory

The present disclosure belongs to the field of network technologies, and discloses a resource deduction method and apparatus, an intelligent terminal, and a deduction server. The method includes: sending a rule obtaining request for a deduction rule of a user-specified deduction item to the deduction server; receiving the deduction rule returned by the deduction server; calculating a second resource value that is obtained after applying the deduction rule to a first resource value associated with the user-specified deduction item; and sending a resource transfer request carrying the second resource value to the deduction server. The present disclosure resolves a problem that a merchant needs to manually calculate expense that is obtained after applying the deduction rule to the first resource, and payment efficiency is relatively low. Expense that is obtained after applying the deduction rule to the first resource is automatically calculated by using an intelligent terminal, and payment efficiency is improved.

Resource deduction method and apparatus, intelligent terminal, and deduction server

Embodiments of the present invention disclose an image chip. The image chip includes: a processor for dividing an image frame into at least two image segments, a read circuit for reading the at least two image segments in a time-division manner, and an image synthesizer for successively performing image synthesis on the at least two image segments according to a time sequence read by the read circuit. The image frame comprises multiple layers and each layer in the multiple layers is a rectangular layer having two first boundaries. Two first boundaries of a first image segment in the at least two image segments correspond to two neighboring boundaries in all the first boundaries of the multiple layers. The image synthesis for each image segment in the at least two image segments comprises image synthesis for all sublayers in the each image segment.

Image synthesis method, image chip, and image device

Embodiments of the present invention disclose an image synthesis method, an image chip, and an image device. The method includes separately obtaining two coordinates, on a first coordinate axis, corresponding to two boundaries that are of each layer in multiple layers of an image frame and that are perpendicular to the first coordinate axis, so as to obtain multiple coordinates corresponding to the multiple layers. The method also includes dividing, by using the multiple coordinates, the image frame into at least two image segments perpendicular to the first coordinate axis; reading, along a direction of the first coordinate axis, the at least two image segments in a time-division manner and according to a scanning sequence. Additionally, the method includes successively performing image synthesis on the at least two image segments according to a time sequence of reading the at least two image segments, so as to generate display data.

Growing community of inventors

Shanghai, China

Jingwei Chen