Advanced Micro Devices Corporation

Globalfoundries Inc.

Globalfoundres Inc.

Jingrong Zhou

David Donggang Wu

James F Buller

Mark W Michael

Akif Sultan

Zhonghai Shi

Ruigang Li

Donna Michael, Legal Representative

Jian Feng Chen

Fred N Hause

A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

Electronic device and method of biasing

Shallow trench isolation silicon-on-insulator (SOI) devices are formed with improved charge protection. Embodiments include an SOI film diode and a Psubstrate junction as a charging protection device. Embodiments also include a conductive path from the SOI transistor drain, through a conductive contact, a metal line, a second conductive contact, an SOI diode, isolated from the transistor, a third conductive contact, a second conductive line, and a fourth conductive contact to a P-doped substrate contact in the bulk silicon layer of the SOI substrate.

Charging protection device

A transistor-based fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fuse structure includes a plurality of transistor-based fuses, and the method begins by selecting, from the plurality of transistor-based fuses, a first target fuse to be programmed for operation in a low-resistance/high-current state, the first target fuse having a first source, a first gate, a first drain, and a first gate insulator layer between the first gate and the semiconductor substrate. The method applies a first set of program voltages to the first source, the first gate, and the first drain to cause breakdown of the first gate insulator layer such that current can flow from the first source to the first gate through the first gate insulator layer, and from the first gate to the first drain through the first gate insulator layer.

Semiconductor device with transistor-based fuses and related programming method

A method of fabricating semiconductor devices begins by providing or fabricating a device structure that includes a semiconductor material and a plurality of gate structures formed overlying the semiconductor material. The method continues by creating light dose extension implants in the semiconductor material by bombarding the device structure with ions at a non-tilted angle relative to an exposed surface of the semiconductor material. During this step, the plurality of gate structures are used as a first implantation mask. The method continues by forming a patterned mask overlying the semiconductor material, the patterned mask being arranged to protect shared drain regions of the semiconductor material and to leave shared source regions of the semiconductor material substantially exposed. Thereafter, the method creates heavy dose extension implants and/or halo implants in the semiconductor material by bombarding the device structure with ions at a tilted angle relative to the exposed surface of the semiconductor material, and toward the plurality of gate structures. During this step, the plurality of gate structures and the patterned mask are used as a second implantation mask.

Method of fabricating semiconductor transistor devices with asymmetric extension and/or halo implants

A fabrication process for a FinFET device is provided. The process begins by providing a semiconductor wafer having a layer of conductive material such as silicon. A whole-field arrangement of fins is then formed from the layer of conductive material. The whole-field arrangement of fins includes a plurality of conductive fins having a uniform pitch and a uniform fin thickness. Next, a cut mask is formed over the whole-field arrangement of fins. The cut mask selectively masks sections of the whole-field arrangement of fins with a layout that defines features for a plurality of FinFET devices. The cut mask is used to remove a portion of the whole-field arrangement of fins, the portion being unprotected by the cut mask. The resulting fin structures are used to complete the fabrication of the FinFET devices.

Method of forming multiple fins for a semiconductor device

A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

Compensating for layout dimension effects in semiconductor device modeling

The techniques and technologies described herein relate to the automatic creation of photoresist masks for stress liners used with semiconductor based transistor devices. The stress liner masks are generated with automated design tools that leverage layout data corresponding to features, devices, and structures on the wafer. A resulting stress liner mask (and wafers fabricated using the stress liner mask) defines a stress liner coverage area that extends beyond the boundary of the transistor area and into a stress insensitive area of the wafer. The extended stress liner further enhances performance of the respective transistor by providing additional compressive/tensile stress.

Method for fabricating a semiconductor device having an extended stress liner

The present invention is directed to an SOI device with charging protection and methods of making same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.

SOI device with charging protection and methods of making same

The halo implant technique described herein employs a halo implant mask that creates a halo implant shadowing effect during halo dopant bombardment. A first transistor device structure and a second transistor device structure are formed on a wafer such that they are orthogonally oriented to each other. A common halo implant mask is created with features that prevent halo implantation of the diffusion region of the second transistor device structure during halo implantation of the diffusion region of the first transistor device structure, and with features that prevent halo implantation of the diffusion region of the first transistor device structure during halo implantation of the diffusion region of the second transistor device structure. The orthogonal orientation of the transistor device structures and the pattern of the halo implant mask obviates the need to create multiple implant masks to achieve different threshold voltages for the transistor device structures.

Method of forming transistor devices with different threshold voltages using halo implant shadowing

The present invention is directed to methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same. In one illustrative embodiment, the method includes forming a plurality of test structures on a semiconducting substrate, each of the test structures having at least one physical dimension that varies relative to the other of the plurality of test structures, at least some of the test structures exhibiting at least some degree of manufacturing-induced corner rounding, forming at least one reference test structure, performing at least one electrical test on the plurality of test structures and on the reference test structure to thereby produce electrical test results, and analyzing the test results to determine an impact of the manufacturing-induced corner rounding on the performance of the plurality of test structures.

Methods of quantifying variations resulting from manufacturing-induced corner rounding of various features, and structures for testing same

The present invention is directed to an SOI device with charging protection and methods of making the same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.

Growing community of inventors

Austin, TX, United States of America

Jingrong Zhou