Renesas Electronics Corporation

Jingo Nakanishi

Issei Kashima

A plurality of IO cells are arranged along an edge portion of a semiconductor chip. Some elements forming a reference voltage generation circuit are arranged in a first corner region of the semiconductor chip. Remaining elements forming the reference voltage generation circuit are arranged in a core region on an inner side of the edge portion of the semiconductor chip. Among a plurality of corner regions, the first corner region is located closest to the remaining elements.

Semiconductor device

To prevent the influence of variations in reference voltage until a power source is activated in a semiconductor device including a reference voltage generating circuit that can be adjusted by trimming data. In a semiconductor device, a reference voltage generating unit generates a first reference voltage adjusted in accordance with trimming data and a second reference voltage that does not depend on the trimming data based on an external power source voltage. A nonvolatile memory operates in accordance with a voltage based on the first reference voltage and stores the trimming data. A power-on reset circuit switches logic levels of a reset signal when the external power source voltage reaches a constant multiple of the second reference voltage at the time of activation of power source. A control circuit causes the reference voltage generating unit to read the trimming data stored in the nonvolatile memory in response to the switching of the logic levels of the reset signal.

Growing community of inventors

Tokyo, Japan

Jingo Nakanishi