Atmel Corporation

Jinglun Eugene Tam

Geoffrey S Gongwer

Srinivas Ramamurthy

James Fahey

Neal Berger

Keith H Gudger

Joe Yu

William Saiki

Steven A Sharp

Boundary Scan integrated circuits are provided with a plurality of new registers between two dedicated pins, Test Data In (TDI) and Test Data Out (TDO) pins. The new registers include an address register and a plurality of test data registers which are addressable by the address register using address-dependent instructions in the instruction register (IR). Instructions for the addressable registers may be steered to the correct register with an ADDLOAD instruction placed in the instruction register followed by an address-dependent instruction. The ADDLOAD instruction makes the address register active between the TDI and TDO pins. Any instruction from a set of address-dependent instructions may be steered to any register handling address-dependent instructions allowing a small number of instructions to be used in a large number of addressable data registers. At the same time non-addressable registers, such as the Boundary Scan register, use address-independent instructions.

Boundary scan system with address dependent instructions

Bulk operation logic circuitry for use in carrying out bulk program, erase, verify and margining operations on nonvolatile memory cells of a PLD, FPGA, flash-based microcontroller, EEPROM, flash memory device or other integrated circuit containing such cells includes a flag register for designating one or more selected blocks of cells to which the bulk operation will be limited. The bulk operation circuitry includes a controller, with a state machine and associated control logic, that distributes system clock signals and provides control signals to an instruction register, the flag register, an address register and one or more data registers to control loading of instructions and data into those registers through a serial input. The state machine is responsive to a mode signal for switching it from a normal user state into a bulk operation state. The use of a flag register allows simplification of the instruction set to register load instructions and basic bulk operation instructions (and a flow through operation using a serial output from the registers), while providing a wide variety of possible block selections for the different bulk operations.

Integrated circuit with flag register for block selection of nonvolatile

An integrated circuit package including a plurality of macrocells for connecting a logic circuit of the package to a plurality of external contacts of the package. At least one of the macrocells has an output driver that is enabled or disabled by a control signal for transmitting or preventing transmission of a logic signal to one of the contacts. The control signal is generated by a logic gate that receives and logically combines an individual output enable signal dedicated to that particular macrocell with a selected signal. One signal that may be selected is a regional output enable signal that is supplied to more than one macrocell. Each macrocell also has a feedback multiplexer selecting one signal to be sent to the logic circuit. Choices include a nonstored logic signal, a stored logic signal from a flip-flop register in the macrocell, a signal applied to the external contact associated with that macrocell, and a signal applied to another external contact associated with a different macrocell. A plurality of contacts are connected to feedback multiplexers in two different macrocells, and at least one contact connects in this manner to separate logic regions of the logic circuit. The flip-flop register in the macrocell has a choice of data inputs selected by another multiplexer from among at least one logic signal from the logic circuit and at least one signal applied to an external contact.

Integrated logic circuit with functionally flexible input/output

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San Jose, CA, United States of America

Jinglun Eugene Tam