Boe Technology Group Co., Ltd.

Ordos Yuansheng Optoelectronics Co., Ltd.

Freescale Semiconductor,inc.

Chinese Academy of Sciences

China Mobile Communications Group Co., Ltd.

China Mobile Communication Co.,ltd Research Institute

Nxp Usa, Inc.

Infineon Technologies Americas Corp.

Jingjing Chen

Edouard D De Fresart

Peilin Wang

Fuyi Cui

Ganming Qin

Lina Wang

Pon Sung Ku

Nanjian Wu

Haiyong Wang

Liang Zhang

Xu Chen

Nan Li

Ang Xiao

Zhao Zhang

Guangyi Liu

Bing Li

Xiaodong Liu

Fang Quan Xie

Edouard De Frésart

Xueying Hou

Xiaoran Zhang

Xuefei Bai

Quanqin Sun

Peng Feng

Wenyi Li

Xuansheng Wang

Dan Jia

Zhiqiang Gao

Xueyong Zhang

Yedong Wang

Xuewei Li

Weiyang Liu

Wenfeng Lou

D Defresart Edouard

An information reporting method, a data transmission method, a user equipment and a network side device are provided. The information reporting method is applied to the user equipment and includes reporting retransmission times information to the network side device.

Information reporting method, data transmission method, user equipment and network side device

The application provides a sintering apparatus, a packaging system for an organic light emitting diode device and a sintering method, belongs to the technical field of organic light emitting diode device and can solve problems of long process time and high cost existed in the existing high temperature sintering process of organic light emitting diode device. The sintering apparatus comprises two sintering chambers capable of being communicated with each other, during operation, the substrate coated with glass cement is first placed into a sealed first sintering chamber to complete a first sintering process; then the substrate is placed into the second sintering chamber to complete a second sintering process. Thus, a time interval between the first sintering process and the second sintering process can be reduced, and no more nitrogen is wasted in transition from the first sintering process to the second sintering process.

Sintering apparatus, packaging system for organic light emitting diode device and sintering method

A measurement gap configuration method and a device are provided. The method includes: sending, by a secondary node, first indication information or second indication information to a master node; receiving, by the master node, the first indication information or the second indication information sent by the secondary node, wherein the first indication information is used to indicate that the secondary node needs to configure a terminal to perform an E-UTRAN inter-frequency measurement, or is used to request the master node to configure a measurement gap, the second indication information is used to indicate that the secondary node does not need to configure a terminal to perform an E-UTRAN inter-frequency measurement, or is used for not requesting the master node to configure a measurement gap.

Measurement gap configuration method and device

A method of fabricating a display panel having a display area and a component installation area substantially surrounded by the display area. The method includes forming one or more organic layers on a base substrate in both the display area and the component installation area; removing the one or more organic layers in at least a first region of the component installation area; forming an encapsulating material layer in at least the first region of the component installation area; and curing the encapsulating material layer.

Display panel having display area and component installation area, method of fabricating display panel having display area and component installation area, and display apparatus

The present disclosure provides a screen printing device, including a printing screen having a printing mesh and a mesh frame, and a squeegee blade, wherein the printing mesh has first and second longitudinal ends, first and second blank areas, and a printing portion with printed patterns between the first and second blank areas, which being movably connected to the mesh frame by a tension adjusting mechanism respectively and being provided with at least one tension sensor respectively approximate to the printing portion, wherein the device further has a control means for receiving a tension measurement value from the tension sensor and compare it with a reference value so as to control the tension adjustment mechanism to adjust the tension in the printing mesh. The disclosure further provides a method for adjusting the tension of the printing mesh of the screen printing device.

Screen printing device and method for adjusting tension in printing mesh thereof

An encapsulation method and an encapsulation device are provided. The encapsulation method comprises: forming a binding agent in an encapsulation region of a display substrate; forming an organic thin film on the binding agent; exerting a pressure on the organic thin film and the binding agent by using a pressure exerting device, wherein the organic thin film is not bound to the pressure exerting device; removing the organic thin film; and providing a cover plate on the binding agent and binding the cover plate with the display substrate by the binding agent.

Encapsulation method and encapsulation device

Embodiments of this disclosure provide an encapsulating material, an encapsulating cover plate, a sintering equipment, a sintering method, and a display apparatus, and relate to the technical field of display. This encapsulating material comprises a leveling auxiliary material, wherein the leveling auxiliary material is used to move upon excitation so as to level the encapsulating material when the encapsulating material is subjected to sintering, and is thus used in the encapsulation of a cover plate to be encapsulated and an encapsulating cover plate.

Encapsulating material, encapsulating cover plate, sintering equipment, sintering method, and display apparatus

A wireless radio-frequency transmission apparatus includes a phase frequency detector, a charge pump, a loop filter and a twin voltage-controlled oscillator. The twin voltage-controlled oscillator includes a first oscillator and a second oscillator. When the twin voltage-controlled oscillator is in a reception mode, the first and the second oscillators are coupled to each other to form a quadrature voltage-controlled oscillator, and the quadrature voltage-controlled oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop to generate quadrature carriers. When the twin voltage-controlled oscillator is in a transmission mode, the first oscillator, the phase frequency detector, the charge pump and the loop filter constitute a phase-locked loop, and the second oscillator performs frequency modulation on transmitted data. The present disclosure can maintain a carrier frequency to be stable during high data rate transmission, and have a relatively short locking time of frequency hopping.

Wireless radio-frequency transmission apparatus

The present disclosure discloses a multi-standard performance reconfigurable I/Q orthogonal carrier generator. The generator may implement a continuously covered I/Q carrier output of 0.1-5 GHz and continuously covered differential signal outputs of 5-10 GHz and 1.5-3 GHz by means of reasonable frequency assignment; also, carrier signals under various frequencies with different loop bandwidths, different phase noises, different power consumption levels and different locking times can be generated by configuring a programmable charge pump (), a loop filter () parameter, a multi-path voltage-controlled oscillator () and a first multiplexer () corresponding thereto, a five-stage-division-by-two frequency division link () and a corresponding second multiplexer () and third multiplexer (), so as to implement generation of a multi-standard performance reconfigurable I/Q orthogonal carrier.

Multi-standard performance reconfigurable I/Q orthogonal carrier generator

A semiconductor device includes a vertical gate electrode in a gate trench in a semiconductor substrate, and a lateral gate electrode over the semiconductor substrate and adjacent the gate trench, where the lateral gate electrode results in improved electrical performance of the semiconductor device. The improved electrical performance includes an improved avalanche current tolerance in the semiconductor device. The improved electrical performance includes a reduced impact ionization under the gate trench. The improved electrical performance includes a reduced electric field under the gate trench. The lateral gate electrode results in an improved thermal stability in the semiconductor device.

Semiconductor device structure for improved performance and related method

Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

Methods of manufacturing trench semiconductor devices with edge termination structures

A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET () to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

Power MOSFET current sense structure and method

Semiconductor device structures and related fabrication methods are provided. An exemplary semiconductor device structure () includes a trench gate structure (), a lateral gate structure (), a body region () having a first conductivity type, a drain region () and first and second source regions () having a second conductivity type. The first and second source regions () are formed within the body region (). The drain region () is adjacent to the body region () and the first source region () is adjacent to the trench gate structure (), wherein a first portion of the body region () disposed between the first source region () and the drain region () is adjacent to the trench gate structure (). A second portion of the body region () is disposed between the second source region () and the drain region (), and the lateral gate structure () is disposed overlying the second portion of the body region ().

Semiconductor device and related fabrication methods

A method is used to form a vertical MOS transistor. The method utilizes a semiconductor layer. An opening is etched in the semiconductor layer. A gate dielectric is formed in the opening that has a vertical portion that extends to a top surface of the first semiconductor layer. A gate is formed in the opening having a major portion laterally adjacent to the vertical portion of the gate dielectric and an overhang portion that extends laterally over the vertical portion of the gate dielectric. An implant is performed to form a source region at the top surface of the semiconductor layer while the overhang portion is present.

Method for forming a vertical MOS transistor

Growing community of inventors

Beijing, China

Jingjing Chen