Gowin Semiconductor Corporation

Lattice Semiconductor Corporation

Other

Guangdong Gowin Semiconductor Corporation, Ltd.

Jinghui Zhu

Jianhua Liu

Diwakar Chopperla

Om P Agrawal

Chienkuang Chen

Ning Song

Grant Thomas Jennings

Kuang Chi

San-Ta Kow

Ju Shen

Xiaozhi Lin

Tianping Wang

Zhenyu Gu

Tianxin Wang

Ji Zhao

Jock F Tomlinson

Jiyong Zhang

Bin Gao

Allan Thomas Davidson

Tun Jun Gao

Tong-Sheng Wang

Jin Ni

A programmable semiconductor system includes a programmable integrated circuit ('PIC') and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes configurable logic blocks (“LBs”), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (“BDP”) containing default configuration data (“DCD”) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.

Method and system for enhancing programmability of a field programmable gate array

A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.

Method and apparatus for providing multiple power domains in a programmable semiconductor device

A programmable integrated circuit device able to be selectively programmed to perform one or more logic functions includes multiple configurable logic blocks ('LBs'), routing fabric, and a nonvolatile memory (“NVM”). While the configurable LBs are able to be selectively programmed to perform one or more logic functions, the routing fabric selectively routes information between the configurable LBs and input/output ports based on a routing configuration signals. The NVM, such as magnetoresistive random access memory (“MRAM”), phase-change memory, or ferroelectric RAM (“FeRAM”), is flexibly organized to contain a configuration NVM storage and a user NVM storage, wherein the user NVM storage is a word addressable memory capable of facilitating random memory access.

Method and system for providing word addressable nonvolatile memory in a programmable logic device

A semiconductor device provides logic operations utilizing low-power memory blocks ('LMBs') for power conservation. An LMB, in one embodiment, includes a first nonvolatile memory (“NVM”), a second NVM cell, and an LMB output terminal. The first NVM cell contains an NVM transistor able to store one (1) bit of first value persistently. The second NVM cell is configured to persistently store one (1) bit of second value which is opposite logic value of the first value. The LMB output terminal, coupled to a drain terminal of first NVM cell and a source terminal of second NVM cell, is operable to provide an output value in accordance with the first value.

Methods and apparatus for providing a low-power memory block using a pair of nvm cells

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer (“SerDes”) region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Method and system for organizing programmable semiconductor device into multiple clock regions

One embodiment of the present invention discloses a two-phase configuration process ('TCP') to configure a field-programmable gate array (“FPGA”) to include a configurable microcontroller unit (“CMU”) during a phase I configuration and configuring the CMU during a phase II configuration. TCP, in one aspect, is able to receive first configuration data from a first external storage location via a communication bus. After storing the first configuration data in a first configuration memory for configuring FPGA to contain a CMU for the phase I configuration, second configuration data with MCU attributes is obtained from a second external storage location via the communication bus. The second configuration data is subsequently stored in a second configuration memory for programming the CMU for the phase II configuration.

Method and system for providing programmable microcontroller unit (MCU) using two-phase configuration process

A programmable semiconductor device contains a wireless communication block ('WCB') capable of facilitating wirelessly field programmable gate array (“FPGA”) programming download as well as functional logic implementation. In one aspect, WCB detects an FPGA access request for initiating an FPGA reconfiguration from a remote system via a wireless communications network. Upon receiving a configuration bitstream for programming the FPGA via the wireless communications network, the configuration bitstream is forwarded from WCB to a configuration download block (“CDB”) for initiating a configuration process. CDB subsequently programs at least a portion of configurable logic blocks (“LBs”) in FPGA in response to the configuration bitstream.

Method and system for providing wireless FPGA programming download via a wireless communication block

An integrated circuit ('IC') module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.

Method and apparatus for providing field-programmable gate array (FPGA) integrated circuit (IC) package

A programmable integrated circuit ('PIC') device includes configurable logic blocks ('LBs'), routing connections, and configuration memory for performing user defined programmed logic functions. Each configurable LB, in one example, includes a set of lookup tables ('LUTs') and associated registers. The LUTs, for example, are configured to generate one or more output signals in accordance with a set of input signals. The registers are arranged so that each register corresponds to one LUT. In one embodiment, a group of registers, instead of assigning to a group of LUTs across multiple configurable LBs, is allocated or configured as embedded signature registers in PSD. For example, a first register which corresponds or physically situated in the vicinity of first LUT can be designated as an embedded signature register for storing a fixed value or signature information for facilitating device or IC identification.

Method and system for providing FPGA device identification via a set of embedded signature registers

A system contains a field-programmable gate array ('FPGA'), a controller, and a non-volatile memory ('NVM') for providing user-defined logic functions. In one aspect, the controller, having a serial peripheral interface (&#x201c;SPI&#x201d;) port, is capable of processing information based on execution of instructions. NVM, having a memory SPI port, is configured to store configuration data persistently. FPGA includes multiple configurable logic blocks (&#x201c;LBs&#x201d;) configured to be selectively programmed to perform one or more user-defined logic functions in accordance with the configuration data. FPGA, in one embodiment, includes a master SPI (&#x201c;MSPI&#x201d;) port which is used to couple to the memory SPI port of NVM and a slave SPI (&#x201c;SSPI&#x201d;) port which is used to couple to SPI port of controller.

Method and system for accessing a nonvolatile memory via SPI ports

Method and apparatus for providing multiple power domains to a programmable semiconductor device

A programmable semiconductor system includes a programmable integrated circuit ('PIC') and storage capable of facilitating a multi-boot with backup default configuration ('MBC') process. The PIC, in one embodiment, includes configurable logic blocks (&#x201c;LBs&#x201d;), routing connections, and a configuration memory for performing logic functions. The storage includes a first and a second memory. While the first memory stores a user configuration data representing user-defined logic functions, the second memory stores a backup default page (&#x201c;BDP&#x201d;) containing default configuration data (&#x201c;DCD&#x201d;) for programming or booting PIC to its default setting when the user configuration data fails to boot or program PIC. In one aspect, the user configuration data contains the address of the second memory containing DCD.

Method and system for enhancing programmability of a field-programmable gate array

A programmable integrated circuit device able to be selectively programmed to perform one or more logic functions includes multiple configurable logic blocks ('LBs'), routing fabric, and a nonvolatile memory ('NVM'). While the configurable LBs are able to be selectively programmed to perform one or more logic functions, the routing fabric selectively routes information between the configurable LBs and input/output ports based on a routing configuration signals. The NVM, such as magnetoresistive random access memory (&#x201c;MRAM&#x201d;), phase-change memory, or ferroelectric RAM (&#x201c;FeRAM&#x201d;), is flexibly organized to contain a configuration NVM storage and a user NVM storage, wherein the user NVM storage is a word addressable memory capable of facilitating random memory access.

A configurable semiconductor device ('CSD') is organized in four (4) quadrants able to perform user-defined logic functions via a clock fabric. The first quadrant, in one embodiment, includes a first serializer and deserializer ('SerDes') region and a bank0 region for data processing. The second quadrant includes a second SerDes region and a bank5 region and the third quadrant contains a bank3 region and a bank4 region. The fourth quadrant includes a bank1 region and a bank2 region. The clock fabric is configured to provide a set of programmable or selectable clock signals with different clock speeds to various regions within the CSD.

Methods and apparatus for organizing a programmable semiconductor device into multiple clock regions

One embodiment of the present invention discloses a two-phase configuration process ('TCP') to configure a field-programmable gate array ('FPGA') to include a configurable microcontroller unit (&#x201c;CMU&#x201d;) during a phase I configuration and configuring the CMU during a phase II configuration. TCP, in one aspect, is able to receive first configuration data from a first external storage location via a communication bus. After storing the first configuration data in a first configuration memory for configuring FPGA to contain a CMU for the phase I configuration, second configuration data with MCU attributes is obtained from a second external storage location via the communication bus. The second configuration data is subsequently stored in a second configuration memory for programming the CMU for the phase II configuration.

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San Jose, CA, United States of America

Jinghui Zhu