Changxin Memory Technologies, Inc.

Jinghao Wang

Xin Xin

Junbo Pan

Jun Xia

Qiang Wan

Sen Li

Tao Liu

Kangshu Zhan

Penghui Xu

Embodiments provide a method for fabricating a contact structure and a contact structure. The method for fabricating a contact structure includes: providing a substrate, and sequentially arranging a first polysilicon layer and a first mask layer on a surface of the substrate; performing a first etching process on the first polysilicon layer and the first mask layer to form a stepped structure where a width of the first mask layer is smaller than a width of the first polysilicon layer; performing a second etching process on the substrate by using the first polysilicon layer as a mask to form a trench; depositing a second polysilicon layer in the trench, a top of the second polysilicon layer being not higher than a bottom of the first mask layer; and performing an annealing process to form the contact structure.

Method for fabricating contact structure and contact structure

A method for forming a semiconductor structure includes: a substrate is provided, in which active areas arranged in a matrix and isolation structures for isolating active areas from each other are formed in substrate, a first direction is a column direction of matrix and a second direction is a row direction of matrix; a conductive layer is formed on substrate; at least conductive layer is etched to form a plurality of bit line grooves extending along first direction and arranged along second direction and a plurality of conductive lines extending along first direction and arranged along second direction; a bit line structure is formed in each bit line groove, in which a gap is formed between bit line structure and each of two sides of a respective one of bit line grooves; and conductive lines are etched along second direction to form conductive pillars serving as storage node contact structures.

Method for forming semiconductor structure and semiconductor structure

A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.

Mask structure, semiconductor structure and methods for manufacturing same

Embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same. The manufacturing method includes: providing a substrate and bit line structures on the substrate; forming a first isolation layer, the first isolation layer being located on side walls of the bit line structures and on the substrate; forming a second isolation layer, the second isolation layer covering the first isolation layer located on the side walls of the bit line structures, and exposing the first isolation layer located on the substrate; removing the first isolation layer exposed by the second isolation layer and part of the first isolation layer below the second isolation layer, so that remaining of the first isolation layer is recessed compared to the second isolation layer toward the side walls of the bit line structures to form a groove.

Method for manufacturing a semiconductor structure using isolation layers for etching the trenches in a substrate

Provided are a semiconductor structure and a method for forming same. The method includes the following operations. Active areas and first isolation structures disposed at intervals are provided. Second isolation structures located between adjacent active areas are provided, and top surfaces of the second isolation structures are higher than or flush with top surfaces of the active areas. A mask layer are formed, pattern openings of which expose part of the top surfaces of the active areas, and the second isolation structures are located at two opposite sides of part of the active areas. The part of the active areas exposed by the pattern openings and part of the first isolation structures are etched to form intermediate grooves at least exposing part of surfaces of the active areas. Bit line structures are formed, which are electrically connected to top surfaces exposed by the intermediate grooves.

Method for forming a semiconductor structure having second isolation structures located between adjacent active areas

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate including a peripheral region, wherein the peripheral region includes a wire lead-out area, and the substrate is arranged with a plurality of discrete bit line structures; a dielectric layer formed between the adjacent bit line structures, wherein the peripheral region is arranged with a first contact hole; a wire lead-out area with a second through hole; a filling layer filling part of a first contact hole, wherein a remaining part of the first contact hole is defined as a first through hole; a first conductive layer located in the first through hole and the second through hole; and a conductive connecting wire located over the dielectric layer and being in contact with the first conductive layer in the wire lead-out area.

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Hefei, China

Jinghao Wang