Marvell International Limited

Lsi Corporation

Maxtor Corporation

Seagate Technology Incorporated

Marvellworld Trade Ltd.

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Jingfeng Liu

Hongwei Song

Mats Oberg

Zachary A Keirn

Jin Xie

Bin Ni

Haotian Zhang

Yuan Xing Lee

Lingyan Sun

Wooi-Kean Lee

Jinghuan Chen

George Mathew

Yu Liao

Zining Wu

Shaohua Yang

Richard Rauschmayer

Bernardo Rub

Jongseung Park

Scott M Dziak

Toai Doan

Rose Shao

Raymond Pavlak, Jr

Pei-hui Zheng

Steve Aronson

Bradley D Seago

Hoatian Zhang

Peihui Zheng

Sal Citta

Various embodiments of the present invention provide systems and methods for calibrating a data processing circuit. For example, a method for calibrating a data processing circuit is discussed that includes providing a digital filter, providing a detector circuit, and providing an analog filter. Operation of the digital filter is at least in part governed by filter taps that correspond to a filter tap constraint value. Operation of the detector circuit is at least in part governed by a target parameter. Operation of the analog filter is at least in part governed by an analog parameter that is one of a plurality of analog parameters. The methods further include selecting a target parameter, and calculating the filter tap constraint value based on the target parameter. Combinations of the target parameter, the calculated filter tap constraint value, and each of the plurality of analog parameters are applied to identify the analog parameter.

Systems and methods for filter constraint estimation

Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the taps such that a magnitude of a Nyquist response of the digital finite impulse response filter remains within a constraint range.

Nyquist constrained digital finite impulse response filter

A method and device for determining frequency error to extend the pull-in range of a timing recovery circuit for a storage device such as an optical disc drive. A code associated with a storage format of the storage device is detected, and the distance between occurrences of the code is determined. The calculated distance is compared with the expected distance to determine the difference. Based on the difference, the frequency error is determined.

Method and device for increased pull-in range of a timing recovery circuit for storage devices

Aspects of the disclosure provide a method. The method includes boosting a portion of frequency components of a digital signal that is converted from an analog signal based on a clock signal, generating a decision signal based on the boosted digital signal, generating a timing error signal based on the boosted digital signal and the decision signal, and filtering the timing error signal to generate a voltage signal to control a voltage controlled oscillator to generate the clock signal.

Limit equalizer output based timing loop

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes first and second data detectors and an error cancellation circuit. The first data detector is operable to perform a data detection process on a first signal derived from a data input to yield a detected output. The second data detector circuit is operable to perform a data detection process on a second signal derived from the data input to yield a second detected output. The error cancellation circuit is operable to combine a first error signal derived from the detected output with a second error signal derived from the second detected output to yield a feedback signal. The feedback signal is operable to modify the data input during a subsequent period.

Low latency multi-detector noise cancellation

A method in a signal processor includes equalizing, with an equalizer of the signal processor, a signal corresponding to data read from a storage medium to generate an equalized signal, determining a signal level of the equalized signal, determining an expected signal level of the equalized signal, performing a comparison between the signal level of the equalized signal and the expected signal level, adjusting, after the equalized signal is output from the equalizer, an amplitude of the equalized signal by an amount determined based on the comparison of the signal level of the equalized signal and the expected signal level, and decoding the equalized signal after adjusting the amplitude of the equalized signal.

Detector for high frequency amplitude modulation distortion

Aspects of the disclosure provide a method for detecting land pre-pits. The method includes detecting, based on a land pre-pit threshold, a land pre-pit data stream from a signal responsive to land pre-pits on an optical medium, comparing a characteristic of the detected land pre-pit data stream in a specific number of wobble periods with a pre-determined land pre-pit characteristic in the specific number of wobble periods, and adjusting the land pre-pit threshold based on the comparison.

Method and apparatus for detecting land pre-pits

A circuit includes a converter that samples a signal read from a storage medium to generate a sample. The signal includes a physical address of data read from a track on the storage medium. A timing control device generates a clock signal based on a deviation of the track from a reference line. A scaling device generates a scale factor based on the clock signal. A multiplier multiplies the sample by the scale factor to generate a scaled sample. An integrator integrates the scaled sample over a period of the clock signal to generate a resultant value. A comparator compares the resultant value to a threshold to generate an output. The output indicates whether no phase imperfection exists in the scaled sample. A decoder, based on the output of the comparator, decodes the resultant value to obtain the physical address of the data.

Method and circuit for decoding a sample of a signal read from a storage medium to obtain a physical address of data on the storage medium

Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target.

Systems and methods for adaptive target search

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes: a data detector circuit, a calibration circuit, and an enable circuit. The data detector circuit is operable to apply a data detection algorithm to a data input to yield a detected output based at least in part on control values. The calibration circuit operable to update the control values based at least in part on the data input, the detected output, and a calibration circuit enable. The calibration circuit enable is generated by the enable circuit based at least in part on the detected output.

Systems and methods for reliability assisted noise predictive filtering

An offset correction is automatically determined and routinely updated to reduce or eliminate data retrieval errors that may be caused by low level distortion in optical disc data storage recording, re-recording and retrieval system. An offset control loop is provided for reading information from a modulated wobble signal with which the data is recorded to an optical disc data storage medium to provide detection of an offset and correction of that offset to facilitate implementation of precise timing synchronization and/or encoded information contact in the system. The offset detector measures a wobble signal and mathematically converts detected information regarding the measured wobble signal to an offset correction by integrating the wobble signal over a specific time interval and comparing the integrated value to an expected integrated value. The integration may be performed over at least one period of the sinusoidal wobble signal, and the correction added to the wobble signal.

Offset loop for wobble

Method and device for increased pull-in range of timing recovery circuit for storage devices

A signal corresponding to data read from an optical storage medium is equalized to generate an equalized signal. A signal level of the equalized signal is determined, and an expected signal level of the equalized signal without high frequency distortion is determined. A comparison between the signal level of the equalized signal and the expected signal level is performed, and an amplitude of the equalized signal is adjusted based on the comparison of the actual signal level of the equalized signal and the expected signal level. The equalized signal is decoded after adjusting the amplitude of the equalized signal.

A circuit including a wobble signal phase imperfection detector configured to detect and correct a phase transition imperfection in a first scaled wobble signal sample. The wobble signal phase imperfection detector includes an integrator configured to integrate the first scaled wobble signal sample over substantially a half-period portion of the wobble clock signal, and a selector configured to select as an output either i) the first scaled wobble signal sample integrated over substantially one period of the wobble clock signal or ii) the first scaled wobble signal sample integrated over substantially the half-period portion of the wobble clock signal, wherein selection of the first scaled wobble signal sample integrated over substantially one period of the wobble clock signal indicates that the phase transition imperfection does not exist with the first scaled wobble signal sample.

HD DVD wobble detection circuit

A system for removing low frequency offset distortion from a digital signal, the system comprising an analog-to-digital converter to convert an analog frequency signal associated with an optical storage medium to a digital frequency signal; an equalizer to equalize the digital frequency signal; an estimator to estimate a low frequency offset distortion of the digital frequency signal; a compensator to substantially cancel the low frequency offset distortion of the digital frequency signal from the equalized digital frequency signal using the estimate; and a decoder to decode the equalized digital frequency signal having the low frequency offset distortion substantially cancelled therefrom.

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Longmont, CO, United States of America

Jingfeng Liu