Apple Inc.

Jingfei Kong

Ralph Clay Taylor

Michael Andrew Mang

Jason David Carroll

Andrew M Havlir

Jeffrey T Brady

Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry and shader circuitry configured to execute graphics programs. Control circuitry may: generate object shader work and mesh shader work for the shader circuitry, receive output information generated by a mesh shader that indicates a number of vertices and primitives to be output by the mesh shader, allocate, based on the output information and after execution of at least a portion of the mesh shader, a region of the buffer circuitry for storage of the vertices to be output by the mesh shader, and store the vertices output by the mesh shader in the allocated region. Disclosed techniques may advantageously provide efficient use of limited buffer resources.

Resource allocation for mesh shader outputs

Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry, shader circuitry configured to execute graphics programs, including mesh shaders that store output data in the buffer circuitry, and primitive processing circuitry configured to read data from buffer circuitry and process the data, including to cull primitives that are not visible in a graphics frame. Vertex control circuitry may receive: first signaling from the primitive processing circuitry that indicates whether the primitive processing circuitry is waiting for data from the buffer circuitry and second signaling from the shader circuitry that indicates whether the shader circuitry is blocked waiting for allocation in the buffer circuitry. The vertex control circuitry may adjust distribution of mesh shader work to the shader circuitry based on the first signaling and the second signaling.

Mesh shader work distribution

Techniques are disclosed relating to distributing work from compute kernels using distributed parser circuitry. In some embodiments, a master parser is configured to communicate with distributed parsers over a communications fabric. In some embodiments, the master parser generates batches of compute workgroups from a compute kernel and assigns batches to ones of the distributed workload parser circuits. In some embodiments, based on an indicated number of sequential workgroups to send to the same distributed workload parser, the master parser selects a distributed parser to receive a set of batches and avoids selecting a distributed workload parser whose queue would be filled by the batches. In some embodiments, this may avoid stalling for a kernel terminate command. In some embodiments, the master parser may adjust a batch size to avoid filling a distributed parser's queue. In some embodiments, the distributed parsers may use similar techniques when sending work to shader units.

Growing community of inventors

Orlando, FL, United States of America

Jingfei Kong