Cavium, Inc.

Lightelligence Pte. Ltd.

JingDong Deng

Maurice B Steinman

Huaiyu Meng

Cheng-Kuan Lu

Ronald Gagnon

Yelong Xu

Yichen Shen

Jonathan Terry

Scott E Meninger

Arash Hosseinzadeh

Omer O Yildirim

Gilbert Hendry

Yanfei Bai

Jianhua Wu

Longwu Ou

Mike Evans

Jonathan K Brown

An optoelectronic computing system includes a first semiconductor die having a photonic integrated circuit (PIC) and a second semiconductor die having an electronic integrated circuit (EIC). The PIC includes optical waveguides, in which input values are encoded on respective optical signals carried by the optical waveguides. The PIC includes an optical copying distribution network having optical splitters. The PIC includes an array of optoelectronic circuitry sections, each receiving an optical wave from one of the output ports of the optical copying distribution network, and each optoelectronic circuitry section includes: at least one photodetector detecting at least one optical wave from the optoelectronic operation. The EIC includes electrical input ports receiving respective electrical values. The first semiconductor die and the second semiconductor die are electrically coupled in a controlled collapse chip connection, with the electrical output port of the PIC connected to one of the electrical input ports of the EIC.

Optoelectronic computing systems

A system including at least one input optical waveguide configured to receive an optical wave, at least one digital input port configured to receive a series of digital input values, each digital input value including two or more bits, and an optical modulator coupled to the input optical waveguide. The optical modulator includes an optical waveguide portion that includes multiple optical waveguide segments associated with diode sections positioned along the optical waveguide segments, in which the diode sections are configured to apply different respective modulation contributions to an optical wave propagating through the optical waveguide portion.

Optical modulation for optoelectronic processing

A system includes a first unit configured to generate a plurality of modulator control signals, and a processor unit. The processor unit includes: a light source or port configured to provide a plurality of light outputs, and a first set of optical modulators coupled to the light source or port and the first unit. The optical modulators in the first set are configured to generate an optical input vector by modulating the plurality of light outputs provided by the light source or port based on digital input values corresponding to a first set of modulator control signals in the plurality of modulator control signals, the optical input vector comprising a plurality of optical signals. The processor unit also includes a matrix multiplication unit that includes a second set of optical modulators. The matrix multiplication unit is coupled to the first unit, and is configured to transform the optical input vector into an analog output vector based on a plurality of digital weight values corresponding to a second set of modulator control signals in the plurality of modulator control signals applied to the second set of optical modulators. At least one optical modulator of at least one of the first set of optical modulators or the second set of optical modulators is configured to modulate an optical signal based on a first modulator control signal among the plurality of modulator control signals, and the first unit is configured to shape the first modulator control signal to include bandwidth-enhancement associated with a change in amplitude associated with a corresponding change in successive digital values corresponding to the first modulator control signal.

An integrated circuit interposer includes a semiconductor substrate layer; a first metal contact layer including a first metal contact section that includes metal contacts arranged for electrically coupling to a first semiconductor die in a controlled collapsed chip connection, and a second metal contact section that includes metal contacts arranged for electrically coupling to a second semiconductor die in a controlled collapsed chip connection. A first patterned layer includes individually photomask patterned metal path sections. A second patterned layer includes individually photomask patterned waveguide sections, including a first waveguide that crosses at least one boundary between individually photomask patterned waveguide sections. A first modulator is coupled to the first waveguide for modulating an optical wave in the first waveguide based on an electrical signal received at a first metal contact in the first metal contact section, and a second modulator is coupled to the first waveguide for modulating the optical wave based on an electrical signal received at a second metal contact in the first metal contact section or the second metal contact section.

Optoelectronic computing platform

A method and apparatus select an optimal frequency band of a plurality of frequency bands of a multi-band voltage-controlled oscillator (VCO) to achieve a particular output frequency from the multi-band VCO. The optimal frequency band is selected, automatically, based on performing a one-point calibration phase followed by a multi-point calibration phase. The one-point calibration phase produces an initial frequency band selection and the multi-point calibration phase selects the optimal frequency band from a group of frequency bands including the initial frequency band selection, a higher frequency band consecutively higher in frequency relative to the initial frequency band selection, and a lower frequency band consecutively lower in frequency relative to the initial frequency band selection.

Method and apparatus for multi-band voltage-controlled oscillator (VCO) band selection

A frequency divider circuit comprises a first divider chain including at least one first divider cell and a second divider chain coupled to the first divider chain to form an extendable divider chain. The second divider chain includes at least one second divider cell with a respective reset control. An effective length of the extendable divider chain may be altered, dynamically, via the respective reset control. Altering the effective length, dynamically, enables a division ratio of the frequency divider circuit to be changed, dynamically. The frequency divider circuit may be advantageously employed by applications that rely upon a dynamic division ratio, such as a fractional-N (frac-N) phase-locked loop (PLL).

Frequency divider

A bandgap reference (BGR) circuit and method generates a constant voltage reference that is stable over temperature variations. The BGR circuit is composed of a proportional to absolute temperature (PTAT) stage, a complementary to absolute temperature (CTAT) stage, and an output stage interposed between the PTAT stage and the CTAT stage. The PTAT stage is configured to produce a PTAT current and the CTAT stage is configured to produce a CTAT current. The BGR circuit is configured to mirror the PTAT current and mirror the CTAT current to produce a mirrored PTAT current and a mirrored CTAT current in the output stage and the output stage is configured to combine the mirrored PTAT current and the mirrored CTAT current to generate the constant voltage reference.

Method and circuit for low voltage current-mode bandgap

An example embodiment disclosed herein enables at least one frequency divider chain of a multiphase divider circuit to ensure proper phase relations after multiple frequency divisions. Another example embodiment enables a unique reset sequence to maximize a timing margin for reset signals of the at least one frequency divider chain and, thus, maximizes a bandwidth of the multiphase divider circuit.

Multi-phase divider

A low drop-out voltage regulator includes an error amplifier that generates an amplified error voltage, the error amplifier including a first input for receiving a reference voltage, a second input for receiving a feedback voltage, a bias terminal for receiving an adaptive bias current, and an output. A pass gate providing an output voltage includes a first input connected to a supply voltage and a second input connected to the error amplifier output. A feedback network generating the feedback voltage includes a first terminal connected to the output of the pass gate and a second terminal connected to the second input of the error amplifier. An adaptive bias network providing the adaptive bias current includes a first transistor connected to the bias terminal of the error amplifier, a second transistor connected to the first transistor as a current mirror, and a third transistor connected in parallel with the pass gate.

Voltage regulator with adaptive bias network

In an embodiment, a voltage-controlled oscillator circuit includes a gain element and an LC resonator coupled with the gain element, the LC resonator including an inductor section and a capacitor section. The capacitor section has at least two branches connected in parallel and a voltage control input for tuning the LC resonator. Any of the at least two branches is selected from the group of DC-coupled and AC-coupled. Characteristics of the two branches and bias voltages of the AC-coupled branches are selected to provide a tuning curve of the voltage-controlled oscillator circuit that is approximately linear.

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Acton, MA, United States of America

JingDong Deng