Qualcomm Incorporated

Texas Instruments Corporation

Advanced Micro Devices Corporation

National Semiconductor Corporation

Jingcheng Zhuang

Xinhua Chen

Robert Bogdan Staszewski

Khurram Waheed

Xiaohua Kong

Yiwu Tang

Frederic Bossu

Lai Kan Leung

Nam Dang

Miao Li

Ravi Sridhara

Jong Min Park

Animesh Paul

Khurram Muhammad

Gurkanwal Singh Sahota

Bhushan Shanti Asuri

Tirdad Sowlati

Jeremy Darren Dunworth

Zhi Zhu

Emerson S Fang

Shrenik Patel

Francesco Gatta

Terrence Brian Remple

Dongmin Park

Roman Staszewski

Marco Zanuso

Tsai-Pi Hung

Yunliang Zhu

Rajeev Jain

Yue Chao

Mohammad Elbadry

Bruce A Doyle

Jianyun Hu

Wei Wang

William Knox Ladd

Glenn Murphy

Xiaoliang Bai

Girish Koppassery

Mong Chit Wong

Behnam Amelifard

Yan Hu

Madhukar Vallabhaneni

Shih-Chieh Hsin

Med Nariman

Jing Kang

Thomas Casimir Murphy

Praveen Sampath

Nam Van Dang

A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal.

System and method for maintaining local oscillator (LO) phase continuity

An apparatus comprising a transmit path, a plurality of local oscillators and a control unit. The control unit may be configured to: receive an upcoming resource block (RB) allocation; determine whether the upcoming RB allocation is the same as the current RB allocation; in response to determining that the upcoming RB allocation is different than the current RB allocation: select an unused LO of the plurality of LOs; determine whether a number of allocated RBs associated with the upcoming RB allocation is greater than a threshold; and in response to determining that the number of allocated RBs associated with the upcoming RB allocation is not greater than the threshold, tune the selected LO to a frequency corresponding to the upcoming RB allocation.

Methods and apparatus for a transmit path with frequency hopping phase locked loop

A phase frequency detector (PFD) isolates supply (e.g., voltage supply) to a reference path and a feedback path of a phase locked loop (PLL) such that the power supply to the reference path is independent of the power supply to the feedback path. This isolation improves linearity. In one instance, the PFD includes a supply voltage, one or more switches, a reference capacitor and a feedback capacitor. The reference capacitor is selectively coupled to the supply voltage via the one or more switches and the feedback capacitor is selectively coupled to the supply voltage via the one or more switches.

Phase frequency detector linearization using switching supply

An electronic apparatus is disclosed that implements a distributed differential interconnect. In an example aspect, the electronic apparatus includes a first endpoint having a first differential connection interface and a second endpoint having a second differential connection interface. The electronic apparatus also includes a differential interconnect coupled between the first differential connection interface and the second differential connection interface. The differential interconnect includes a plus pathway and a minus pathway. The plus pathway extends between the first differential connection interface and the second differential connection interface, with the plus pathway including multiple plus conductors. The minus pathway extends between the first differential connection interface and the second differential connection interface, with the minus pathway including multiple minus conductors.

Distributed differential interconnect

A master-slave level shifter array includes an asymmetric master level shifter having a predefined output state that produces an enable signal to drive an array of symmetric slave level shifters during a power collapse. As a result, the slave level shifter array has a reliable output state during a power collapse, while also providing wafer area savings due to their small symmetric characteristics.

Master-slave level shifter array architecture with pre-defined power-up states

A phase locked loop has a frequency divider included in a feedback path. The frequency divider generates a first output and a delayed output. The phase locked loop also includes a charge pump to generate an output current based on the first output and the delayed output of the frequency divider.

Fractional-N phase locked loop delta sigma modulator noise reduction using charge pump interpolation

A clock distribution architecture is provided in which the output clock signals from a plurality of fractional-N PLLs have a known phase relationship because each fractional-N PLL is configured to commence a phase accumulation responsive to a corresponding edge of a reference clock signal.

System-on-a-chip clock phase management using fractional-N PLLs

A phase continuity architecture is provided to maintain the phase continuity for a post divider output signal from a post divider that post divides a PLL output signal. A pulse swallower removes a pulse from the PLL output signal responsive to an edge is a divided feedback clock signal. A sampler samples the post divider output signal responsive to a detection of the missing pulse to determine a phase relationship between the post divider output signal and the divided feedback clock signal.

PLL post divider phase continuity

Certain aspects of the present disclosure generally relate to methods and apparatus for generating clock signals. For example, certain aspects of the present disclosure provide a clock generation circuit. The clock generation circuit may include a first transistor connected in cascode with a second transistor, wherein an input clock node of the circuit is coupled to gates of the first and second transistors. The clock generation circuit may also include a frequency divider circuit having an input coupled to the input clock node, wherein an output of the frequency divider circuit is coupled to a source of the second transistor, and wherein an output node of the circuit is coupled to drains of the first and second transistors.

Re-timing based clock generation and residual sideband (RSB) enhancement circuit

A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.

Phase continuity technique for frequency synthesis

An integrated circuit (IC) is disclosed for time-to-digital conversion with a latch-based ring. In example aspects, the IC includes a ring, a counter, an encoder, and time-to-digital converter (TDC) control circuitry. The ring includes multiple ring stages and propagates a ring signal between successive ring stages. Each respective ring stage includes latch circuitry to secure a state of the ring signal at the respective ring stage. The ring provides a ring output signal using the latch circuitry of each of the ring stages. The ring is coupled to the counter. The counter increments a counter value responsive to the ring signal and provides a counter output signal based on the counter value. The encoder is coupled to the ring and the counter. The encoder generates a TDC output signal based on the ring and counter output signals. The TDC control circuitry operates the ring responsive to a TDC input signal.

Time-to-digital conversion with latch-based ring

Techniques for accommodating an incoming signal at a front-end receiver via AC-coupling or DC-coupling are described herein. In one aspect, a front-end receiver comprises a differential input with a first data line and a second data line for receiving an incoming signal. The front-end receiver also comprises an AC-coupled switch coupled to the differential input, wherein the AC-coupled switch is configured to both perform high-pass filtering on the incoming signal and offset the filtered incoming signal with a DC-offset voltage if an AC-coupling mode of the receiver is enabled. The front-end receiver further comprises a DC-coupled switch coupled to the differential input, wherein the DC-coupled switch is configured to shift a common-mode voltage of the incoming signal if a DC-coupling mode of the receiver is enabled.

Unified front-end receiver interface for accommodating incoming signals via AC-coupling or DC-coupling

Certain aspects of the present disclosure provide techniques and apparatus for glitch-free bandwidth switching in a phase-locked loop (PLL). One example PLL generally includes a voltage-controlled oscillator (VCO) comprising a first variable capacitive element and a second variable capacitive element and a bandwidth adjustment circuit comprising a first switch in parallel with a resistor of a resistor-capacitor (RC) network. The bandwidth adjustment circuit is configured to open the first switch for a first bandwidth mode, close the first switch in a transition from the first bandwidth mode to a second bandwidth mode, and control a capacitance of the second variable capacitive element based on a voltage of a node of the RC network.

Glitch free bandwidth-switching scheme for an analog phase-locked loop (PLL)

A series of current repeaters with localized feedback is provided. Each current that precedes a subsequent current repeater in the series is configured to receive a feedback current from the subsequent current repeater and generate an error signal accordingly with a differential amplifier so as to reduce current repetition errors that would otherwise result from an offset voltage in the differential amplifier.

Band-gap current repeater

Methods and systems according to one or more embodiments are provided for frequency detection. In an embodiment, a frequency detector is provided that includes a capacitor that discharges or charges responsive to binary states of an input signal.

Systems and methods for frequency detection

Growing community of inventors

San Diego, CA, United States of America

Jingcheng Zhuang