Hefei Core Storage Electronic Limited

Jing Zhang

Qi-Ao Zhu

Xin Wang

Kuai Cao

Wan-Jun Hong

Xu Hui Cheng

Chih-Ling Wang

Tong-Jin Liu

Yang Zhang

Dong Sheng Rao

Kai-Di Zhu

Ya-Lin Zhu

Long Fei Zhang

Ti De Zhang

A power-supply control device and a power test system are disclosed. The power test system includes a memory and a processor. The processor is configured to: obtain at least one power-supply path manner of at least one power-down test device; determine at least one power-supply path interface according to the at least one power-supply path manner; determine at least one electronic switch according to the at least one power-supply path interface; determine at least one target device to be tested; obtain at least one power-down test instruction according to the at least one target device; establish a target power-supply path corresponding to the target device between the at least one power-supply path interface and the at least one electronic switch according to the power-supply path establishment parameter; and at the target power-supply path, perform a power-down operation according to the power-down execution parameter.

Power control device and power test system

A memory polling method, a memory storage device and a memory control circuit unit are provided. The memory polling method includes: detecting a plurality of busy times corresponding to a plurality of physical units when executing a plurality of first commands; counting the busy times corresponding to the physical units to generate a count statistic value, and determine a delay time based on the count statistic value; and transmitting a plurality of status requests to a rewritable non-volatile memory module after the delay time.

Memory polling method, memory storage device and memory control circuit unit

A data storing allocation method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes the following. A plurality of data writing speeds of a plurality of memory units are detected. An initial write volume of each memory unit is determined according to a number of dies in each memory unit. At least one compensation data volume is calculated according to the data writing speeds and the initial write volume of each memory unit. A write data corresponding to a write command is written to the memory units according to the initial write volume of each memory unit and the at least one compensation data volume.

Data storing allocation method, memory storage apparatus and memory control circuit unit

A table management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: storing multiple table groups, wherein each of the table groups includes multiple voltage management tables; detecting a status of the memory storage device; determining one of the table groups as a target table group according to the status of the memory storage device, wherein the target table group includes multiple target voltage management tables; reading data from a rewritable non-volatile memory module by using at least one read voltage level according to at least one of the target voltage management tables.

Table management method, memory storage device and memory control circuit unit

A mapping information recording method for a rewritable non-volatile memory module is provided. The rewritable non-volatile memory module includes multiple physical erasing units, and each of the physical erasing unit includes multiple physical programming units. The mapping information recording method includes: receiving first continuous data from a host system, wherein the host system instructs to store the first continuous data to a first continuous logical address; establishing a continuous mapping table to record a start logical address of the first continuous logical address, a length of the first continuous logical address, and a bitmap; writing the first continuous data into first physical programming units; and marking bits of virtual blocks corresponding to the first continuous logical address in the bitmap as a valid state, numbering the virtual blocks, and recording the numbers into the continuous mapping table.

Mapping information recording method, memory control circuit unit, and memory storage device

A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.

Memory performance optimization method, memory control circuit unit and memory storage device

A memory management method. The memory management method includes: receiving a command from a host system; sending a command sequence corresponding to the command to a rewritable non-volatile memory module; determining a delay time; and sending a plurality of polling commands to the rewritable non-volatile memory module after the delay time.

Memory management method, memory storage device and memory control circuit unit

A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a first write command from a host system; instructing a rewritable non-volatile memory module to perform a first write operation according to the first write command; obtaining first performance information corresponding to the first write operation; and updating threshold information according to the first performance information, wherein the threshold information is configured to determine a type of target data.

Memory management method, memory device, and memory control circuit for improving data classification

A data merging method for flash memory, a flash memory control circuit unit and a flash memory storage device are provided. The disclosure is applicable to a flash memory, an embedded memory device or a solid state drive of 3D structure. The method includes: selecting at least one source physical erasing unit from at least one first physical erasing unit according to a valid data count of the at least one first physical erasing unit and a valid data count of each of a plurality of memory sub-modules; and copying valid data in the at least one source physical erasing unit to at least one destination physical erasing unit to perform a valid data merging operation.

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Province, China

Jing Zhang