United Microelectronics Corp.

Jing-Yin Jhang

Hui-Lin Wang

Chen-Yi Weng

Yu-Ping Wang

Chin-Yang Hsieh

I-Ming Tseng

Yi-Hui Lee

Ying-Cheng Liu

Yi-An Shih

Po-Kai Hsu

Si-Han Tsai

Che-Wei Chang

Hung-Yueh Chen

Yi-Wei Tseng

Ching-Hua Hsu

Chien-Ting Lin

Yu-Tsung Lai

Kun-Ju Li

Chia-Chang Hsu

Bin-Siang Tsai

Chun-Lung Chen

Chia-Lin Lu

Fu-Yu Tsai

Wei-Hao Huang

Tai-Cheng Hou

Chih-Yueh Li

Yi-Yu Lin

Wei-Xin Gao

Kun-Yuan Liao

Yi-Wei Chen

Hung-Chan Lin

Chih-Chien Liu

Chun-Yuan Wu

Jia-Rong Wu

Rai-Min Huang

Kun-Chen Ho

Yi-Syun Chou

Jun Xie

Chang-Min Li

Rung-Yuan Lee

Wei-Jen Wu

Jia-Feng Fang

Wei Chen

Kun-I Chou

Dong-Ming Wu

Ming-Yueh Tsai

Po-Cheng Huang

Yu-Ting Li

Ya-Huei Tsai

Fu-Shou Tsai

Wen-Chin Lin

I-Fan Chang

Ju-Chun Fan

Chih-Hsun Lin

Ya-Jyuan Hung

Meng-Jun Wang

Shun-Yu Huang

Po-kai Hsu

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and form a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Semiconductor device and method for fabricating the same

A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

Method for fabricating semiconductor device including embedded magnetic resistance random access memory

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

A method for fabricating semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, in which the MTJ stack includes a pinned layer on the substrate, a barrier layer on the pinned layer, and a free layer on the barrier layer. Next, a top electrode is formed on the MTJ stack, the top electrode, the free layer, and the barrier layer are removed, a first cap layer is formed on the top electrode, the free layer, and the barrier layer, and the first cap layer and the pinned layer are removed to form a MTJ and a spacer adjacent to the MTJ.

Magnetoresistive random access memory and method for fabricating the same

A magnetic memory device includes a bottom electrode layer, a magnetic tunneling junction (MTJ) stack disposed on the bottom electrode layer, a dielectric cap layer disposed on the MTJ stack, and a metal cap layer disposed on the dielectric cap layer, wherein the metal cap layer comprises a plurality of first metal layers and second metal layers alternately stacked on the dielectric cap layer.

Magnetic memory device and method for forming the same

A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Magnetoresistive random access memory

A semiconductor structure includes a substrate, a first dielectric layer on the substrate, a plurality of memory stack structures on the first dielectric layer, an insulating layer conformally covering the memory stack structures and the first dielectric layer, a second dielectric layer on the insulating layer and filling the spaces between the memory stack structures, a first interconnecting structure through the second dielectric layer, wherein a top surface of the first interconnecting structure is flush with a top surface of the second dielectric layer and higher than top surfaces of the memory stack structures, a third dielectric layer on the second dielectric layer, and a plurality of second interconnecting structures through the third dielectric layer, the second dielectric layer and the insulating layer on the top surfaces of the memory stack structures to contact the top surfaces of the memory stack structures.

Semiconductor structure and method for forming the same

A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

A magnetoresistive random access memory (MRAM) device includes a first array region and a second array region on a substrate, a first magnetic tunneling junction (MTJ) on the first array region, a first top electrode on the first MTJ, a second MTJ on the second array region, and a second top electrode on the second MTJ. Preferably, the first top electrode and the second top electrode include different nitrogen to titanium (N/Ti) ratios.

A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

The high-density MRAM device of the present invention has a second interlayer dielectric (ILD) layer covering the capping layer in the MRAM cell array area and the logic area. The thickness of the second ILD layer in the MRAM cell array area is greater than that in the logic area. The composition of the second ILD layer in the logic area is different from the composition of the second ILD layer in the MRAM cell array area.

High density magnetoresistive random access memory device

A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

A method of fabricating magnetoresistive random access memory, including providing a substrate, forming a bottom electrode layer, a magnetic tunnel junction stack, a top electrode layer and a hard mask layer sequentially on the substrate, wherein a material of the top electrode layer is titanium nitride, a material of the hard mask layer is tantalum or tantalum nitride, and a percentage of nitrogen in the titanium nitride gradually decreases from a top surface of top electrode layer to a bottom surface of top electrode layer, and patterning the bottom electrode layer, the magnetic tunnel junction stack, the top electrode layer and the hard mask layer into multiple magnetoresistive random access memory cells.

Magnetoresistive random access memory and method of manufacturing the same

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Tainan, Taiwan

Jing-Yin Jhang