Microsoft Technology Licensing, LLC

Baidu Online Network Technology (beijing) Co., Ltd.

Beijing Baidu Netcom Science Technology Co., Ltd

Jing Yan

Yuan Wang

Qiang Li

Jingjing Xue

Ning Yu

Feng-Hsiung Hsu

Jiawei Gu

Hao Zhou

Rui Gao

Yunyan Hu

Jin Zhao

Chunshui Zhao

Yingnan Liu

Mingjie Wang

Yaling Zhang

Xiong-Fei Cai

Ning-Yi Xu

Xing Su

Guohao Gong

Xiaoliang Cong

Feng-hsiung Hsu

Shaopeng Song

Xiang Yang

Yongchen Li

Shenglin Qin

Fanduo Kong

Yang Tao

Shewei Deng

Embodiments of the present disclosure disclose a method and apparatus for generating information. A specific embodiment of the method comprises: acquiring associated information of a road to be evaluated for driving difficulty; generating traffic environment information of the road based on the associated information; and inputting the traffic environment information of the road into a driving difficulty evaluation model to obtain a driving difficulty level of the road for an autonomous driving vehicle. The driving difficulty of the road for the autonomous driving vehicle is evaluated, to obtain the driving difficulty level of the road for the autonomous driving vehicle. Thus, based on a driving difficulty level of each road for the autonomous driving vehicle, the autonomous driving vehicle may select a road having a low driving difficulty level to drive.

Method and apparatus for generating information

Technologies pertaining to computing depth images of a scene that includes a mobile object based upon the principle of light falloff are described herein. An infrared image of a scene that includes a mobile object is captured, wherein the infrared image has a plurality of pixels having a respective plurality of intensity values. A depth image for the scene is computed based at least in part upon square roots of respective intensity values in the infrared image.

Generation of depth images based upon light falloff

Accelerator systems and methods are disclosed that utilize FPGA technology to achieve better parallelism and processing speed. A Field Programmable Gate Array (FPGA) is configured to have a hardware logic performing computations associated with a neural network training algorithm, especially a Web relevance ranking algorithm such as LambaRank. The training data is first processed and organized by a host computing device, and then streamed to the FPGA for direct access by the FPGA to perform high-bandwidth computation with increased training speed. Thus, large data sets such as that related to Web relevance ranking can be processed. The FPGA may include a processing element performing computations of a hidden layer of the neural network training algorithm. Parallel computing may be realized using a single instruction multiple data streams (SIMD) architecture with multiple arithmetic logic units in the FPGA.

Field-programmable gate array based accelerator system

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Beijing, China

Jing Yan