Applied Materials, Inc.

Agilent Technologies, Inc.

Jing Tang

Nitin K Ingle

Dongqing Yang

Kedar Sapre

Mei Yin Chang

Wei Liu

Shankar Venkataraman

Christopher Sean Olsen

Paul F Ma

Zheng Yuan

Johanes F Swenberg

Shiyu Sun

Jacob Newman

Tze Wing Poon

Udayan Ganguly

Sunderraj Thirupapuliyur

Vicky U Nguyen

Abhijit Basu Mallick

David P Thompson

Christopher Dennis Bencher

Matthew S Rogers

Xinliang Lu

Chien-Teh Kao

Yi Zheng

Swaminathan T Srinivasan

Zhenbin Ge

Annamalai Lakshmanan

Yoshitaka Yokota

Vikash Banthia

Mingda Wang

Patrick D Perkins

Linlin Wang

Kiran V Thadani

Ajay Bhatnagar

William H McClintock

Maozi Liu

Jennifer Meng Tseng

Elizabeth Carr

Zhefeng Li

Yoshita Yokota

Rossella Mininni

Po-Ta Chen

Swaminathar Srinivasan

David Thompson

A multilayer coating including an adhesion layer; and a protective coating is disclosed. The multilayer coating can be applied to a portion of at least one of a base and a tip of an interface cone. A method of making a coated interface cone is also disclosed.

Multilayer coating for interface cones

An ion transfer device includes a tube, a resistive layer on an inside surface of the tube, and a dielectric layer on the resistive layer. The device defines a conduit providing a transfer path for gas and ions. The conduit is surrounded by the dielectric layer. The dielectric layer protects the resistive layer from the chemical environment in the conduit, while being thin enough to allow charges to pass through the dielectric layer and be dissipated by the resistive layer.

Dielectric coated ion transfer device for mass spectrometry

Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.

Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof

Described are methods of forming a semiconductor device. Certain methods comprises depositing a film comprising manganese nitride over a dielectric; depositing a copper seed layer over the film; and depositing a copper fill layer over the copper seed layer. Also described are semiconductor devices. Certain semiconductor devices comprise a low-k dielectric layer; a manganese nitride layer overlying the low-k dielectric layer; a seed layer selected from a copper seed layer or electrochemical deposition seed layer overlying the manganese nitride layer; a copper layer overlying the copper seed layer.

Methods for manganese nitride integration

The present invention generally relates to a floating gate structure and method of forming the same. The floating gate structure has an upper portion which is wider than a middle portion of the floating gate structure. The upper portion may have a flared, rounded or bulbous shape instead of being pointed or having sharp corners. The reduction in pointed or sharp features of the upper portion reduces the electric field intensity near the upper portion, which decreases current leakage through the interpoly dielectric. The method includes forming a nitride cap on the upper surface of the floating gate structure to assist in shaping the floating gate. The floating gate is then formed using multiple selective oxidation and etching processes.

Floating gates and methods of formation

Described are manganese-containing films, as well as methods for providing the manganese-containing films. Doping manganese-containing films with Co, Mn, Ru, Ta, Al, Mg, Cr, Nb, Ti or V allows for enhanced copper barrier properties of the manganese-containing films. Also described are methods of providing films with a first layer comprising manganese silicate and a second layer comprising a manganese-containing film.

Methods for depositing manganese and manganese nitrides

A method of etching a recess in a semiconductor substrate is described. The method may include forming a dielectric liner layer in a trench of the substrate where the liner layer has a first density. The method may also include depositing a second dielectric layer at least partially in the trench on the liner layer. The second dielectric layer may initially be flowable following the deposition, and have a second density that is less than the first density of the liner. The method may further include exposing the substrate to a dry etchant, where the etchant removes a portion of the first liner layer and the second dielectric layer to form a recess, where the dry etchant includes a fluorine-containing compound and molecular hydrogen, and where the etch rate ratio for removing the first dielectric liner layer to removing the second dielectric layer is about 1:1.2 to about 1:1.

Intrench profile

A method of etching a substrate comprises forming on the substrate, a plurality of double patterning features composed of silicon oxide, silicon nitride, or silicon oxynitride. The substrate having the double patterning features is provided to a process zone. An etching gas comprising nitrogen tri-fluoride, ammonia and hydrogen is energized in a remote chamber. The energized etching gas is introduced into the process zone to etch the double patterning features to form a solid residue on the substrate. The solid residue is sublimated by heating the substrate to a temperature of at least about 100&#xb0; C.

Double patterning etching process

A method of etching silicon oxide from a multiple trenches is described which allows more homogeneous etch rates among trenches. The surfaces of the etched silicon oxide within the trench following the etch may also be smoother. The method includes two dry etch stages followed by a sublimation step. The first dry etch stage removes silicon oxide quickly and produces large solid residue granules. The second dry etch stage remove silicon oxide slowly and produces small solid residue granules in amongst the large solid residue granules. Both the small and large solid residue are removed in the ensuing sublimation step. There is no sublimation step between the two dry etch stages.

Uniform dry etch in two stages

A method of etching silicon-containing material is described and includes a SiConi&#x2122; etch having a greater or lesser flow ratio of hydrogen compared to fluorine than that found in the prior art. Modifying the flow rate ratios in this way has been found to reduce roughness of the post-etch surface and to reduce the difference in etch-rate between densely and sparsely patterned areas. Alternative means of reducing post-etch surface roughness include pulsing the flows of the precursors and/or the plasma power, maintaining a relatively high substrate temperature and performing the SiConi&#x2122; in multiple steps. Each of these approaches, either alone or in combination, serve to reduce the roughness of the etched surface by limiting solid residue grain size.

Smooth SiConi etch for silicon-containing films

Methods of dry etching silicon-containing dielectric films are described. The methods include maintaining a relatively high temperature of the dielectric films while etching in order to achieve reduced solid residue on the etched surface. Partially or completely avoiding the accumulation of solid residue increases the etch rate.

High-temperature selective dry etch having reduced post-etch solid residue

A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.

Invertable pattern loading with dry etch

A method of etching silicon-and-carbon-containing material is described and includes a SiConi&#x2122; etch in combination with a flow of reactive oxygen. The reactive oxygen may be introduced before the SiConi&#x2122; etch reducing the carbon content in the near surface region and allowing the SiConi&#x2122; etch to proceed more rapidly. Alternatively, reactive oxygen may be introduced during the SiConi&#x2122; etch further improving the effective etch rate.

Silicon-selective dry etch for carbon-containing films

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Santa Clara, CA, United States of America

Jing Tang