Intel Corporation

Jing Li

Yongping Fan

Ian A Young

Andrew M Volk

Jeffrey William Waldrip

Amir Bashir

Sridhar Tirumalai

In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control.

Temperature compensated PLL calibration

A mixed signal circuit architecture is disclosed for automatic frequency control and digital temperature compensation in an LC-PLL system. Some embodiments allow for high-volume manufacturing of products such as microprocessors and chipsets, and other circuits that employ LC-PLL technology. In some embodiments, various capacitor loadings can be selected to compensate for variation associated with process, voltage, temperature, and reference frequency. In addition, a multi-leg capacitor bank can be selectively used to further compensate for temperature variation post-lock, in accordance with some embodiments. A programmable timer can be used in some embodiments to allow for loop settling prior to assessing parameters of interest.

Automatic frequency control architecture with digital temperature compensation

A fast lock scheme for phase locked loops and delay locked loops, where apparatus, systems, and methods include a startup circuit that is enabled at the beginning of a startup mode and is disabled upon a phase transition detection in the reference and feedback signals to the phase locked loop or delay locked loop. Further apparatus, systems, and methods enable a first charge pump when a phase transition is detected, and enable a second charge pump when the phase difference between the reference and feedback signals fall within a predetermined range.

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Folsom, CA, United States of America

Jing Li