Taiwan Semiconductor Manufacturing Comp. Ltd.

Jing-Jyu Chou

Ching-Hung Kao

Yi-Sin Wang

Shan-Yun Cheng

Yi-Ting Chen

A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.

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Taichung, Taiwan

Jing-Jyu Chou