Xilinx, Inc.

Intarsia Corporation

Jing Jing

Shuxian Wu

Parag Upadhyaya

Zhaoyin D Wu

Yohan Usthavia Frans

Teruo Sasagawa

Adebabay M Bekele

Xin X Wu

Didem Z Turker Melek

Jane W Sowards

Xuewen Jiang

Parag Upadhyahya

Sunil D Wijeyesekera

Donald C Benson

A chip package and method for fabricating the same are provided that includes an off-die inductor. The off-die inductor is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The redistribution layer is connected to a package substrate to form the chip package.

Chip package with integrated off-die inductor

A transformer includes a first inductor, facing in a first direction and a second inductor, facing in a second direction, the second direction opposite to the first. In one example the first and the second inductors are arranged such that the first inductor's legs extend to an area of the second inductor's head, and the second inductor's legs extend to an area of the first inductor's head.

Opposite-facing interleaved transformer design

Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.

Inductor design in active 3D stacking technology

A capacitor includes a first metal layer over a substrate, a second metal layer over the first metal layer, and first and second cells. Each cell is electrically coupled to first and second buses. Each cell includes first plurality and second plurality of fingers in the first metal layer, and third plurality and fourth plurality of fingers in the second metal layer. The first plurality of fingers extend in a first direction parallel to a top surface of the substrate and are electrically coupled to the first bus. The second plurality of fingers extend in the first direction and are electrically coupled to the second bus. The third plurality of fingers extend in a second direction parallel to the top surface of the substrate and are electrically coupled to the first bus. The second direction is different from the first direction. The fourth plurality of fingers extend in the second direction and are electrically coupled to the second bus.

Systems and methods for providing capacitor structures in an integrated circuit

Apparatus and associated methods relate to automatically generating a data structure representation of an on-chip inductive-capacitive (LC) tank circuit by determining parasitic inductances in each of the segments of conductive paths that connect a main inductor to one or more selectable VCO components such as capacitors and varactors, for example. In an illustrative example, one or more of the selectable VCO components may be arranged, when selected, to form a parallel resonant LC tank with the main inductor. A method may include defining nodes aterminating each of the segments along the conductive paths between the main inductor terminals and a drive circuit. By modelling the paths as multi-port inductors and transformers, resonant frequency of the VCO may be more accurately predicted by simulation.

Multi-port inductors and transformers for accurately predicting voltage-controlled oscillator (VCO) frequency

A capacitor includes a cell array including a plurality of cells and a fine tuning cell electrically coupled to the cell array by a first bus and a second bus. Each cell of the cell array includes a first number of fingers electrically coupled to the first and second bus, and a second number of fingers electrically coupled to the first and second bus. The fine tuning cell includes a third number of fingers electrically coupled to the first and second bus, and a fourth number of fingers electrically coupled to the first and second bus. The directional alignment of the first and second number of fingers is generally perpendicular, the directional alignment of the third and fourth number of fingers is generally perpendicular, and the second number of fingers is different than the fourth number of fingers.

An integrated circuit device is described. The integrated circuit device comprises a substrate; a plurality of metal routing interconnect layers; an inductor formed in at least one metal layer of the plurality of metal routing interconnect layers; and a bottom metal layer between the plurality of metal routing interconnect layers and the substrate; wherein a pattern ground shield is formed in the bottom metal layer. A method of implementing an integrated circuit device is also disclosed.

Circuits for and methods of implementing an inductor and a pattern ground shield in an integrated circuit

An example a semiconductor device includes a first circuit and a second circuit formed in a semiconductor substrate. The semiconductor device further includes a first guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the first guard structure including first discontinuous pairs of n+ and p+ diffusions disposed along a first axis. The semiconductor device further includes a second guard structure formed in the semiconductor substrate and disposed between the first circuit and the second circuit, the second guard structure including second discontinuous pairs of n+ and p+ diffusions disposed along the first axis, the second discontinuous pairs of n+ and p+ diffusions being staggered with respect to the first discontinuous pairs of n+ and p+ diffusions.

Substrate noise isolation structures for semiconductor devices

In an example, a capacitor in an integrated circuit (IC), includes: a first finger capacitor formed in at least one layer of the IC having a first bus and a second bus; a second finger capacitor formed in the at least one layer of the IC having a first bus and a second bus, where a longitudinal edge of the second bus of the second finger capacitor is adjacent a longitudinal edge of the first bus of the first finger capacitor and separated by a dielectric gap; and a first metal segment formed on a first layer above the at least one layer, the first metal segment being electrically coupled to the first bus of the first finger capacitor and increasing a width and a height of the first bus of the first finger capacitor.

Capacitor structure in an integrated circuit

A circuit includes a first finger capacitor having a first bus line coupled to a first plurality of finger elements and a second bus line coupled to a second plurality of finger elements. The first bus line is parallel to the second bus line. The circuit further includes an inductor having a first leg oriented perpendicular to the first bus line and the second bus line. The first leg of the inductor is coupled to a center of the first bus line.

High quality factor inductive and capacitive circuit structure

An inductive device includes an inductor having an inductance associated therewith, and a tuning ring disposed around the inductor. The tuning ring has an inductance associated therewith, wherein the tuning ring is coupled to the inductor to establish a mutual inductance between the tuning ring and the inductor. The inductance of the inductor, the inductance of the tuning ring, and the mutual inductance between the tuning ring and the inductor contribute to a total inductance of the inductive device. The tuning ring is configurable, and is selectively configured to achieve a certain value for the mutual inductance, and a certain value for the inductance of the tuning ring, without changing a footprint of the tuning ring.

Devices and methods for tuning an inductor

An inductor structure implemented within a semiconductor integrated circuit includes a coil of conductive material including at least one turn and a current return encompassing the coil. The current return is formed of a plurality of interconnected metal layers of the semiconductor integrated circuit.

Inductor structure with a current return encompassing a coil

An inductor structure can be implemented within a semiconductor integrated circuit (IC). The inductor structure can include a coil of conductive material having a first terminal and a second terminal each located at an opposing end of the coil. The inductor structure can include a patterned ground shield including a plurality of fingers implemented within an IC process layer located between the coil of conductive material and a substrate of the IC. The inductor structure also can include an isolation wall formed to encompass the coil and the patterned ground shield. The isolation wall can be coupled to one end of each finger.

Integrated circuit inductor having a patterned ground shield

A thin film capacitor and methods for forming the same are described. The capacitor has dielectric layer with a first face, a second face, and at least one edge. The first terminal of the capacitor covers at least a portion of the first face of the dielectric layer, covers at least a portion of one edge of the dielectric layer, and covers a portion of the second face of the dielectric layer. The second terminal of the capacitor covers a portion of the second face of the dielectric layer and does not contact the first terminal. A method for forming the thin film capacitor includes hard baking photoresist at an elevated temperature and anodizing an exposed metal area using the photoresist as a mask.

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San Jose, CA, United States of America

Jing Jing