Taiwan Semiconductor Manufacturing Comp. Ltd.

Jing-Huei Huang

Lun-Kuang Tan

Huicheng Chang

Liang-Yin Chen

Su-Hao Liu

Tsan-Chun Wang

Kuo-Ju Chen

Tung-Po Hsieh

Jie-Huang Huang

Hong-Chih Liu

Ya-Wen Chiu

Wen-Yen Chen

Wei-Han Huang

A method includes forming a resist pattern over a structure, the resist pattern having a trench surrounded by first resist walls extending lengthwise along a first direction and second resist walls extending lengthwise along a second direction perpendicular to the first direction. The method includes loading the structure and the resist pattern into an ion implanter so that a top surface of the resist pattern faces an ion travel direction of the ion implanter. The method includes tilting the structure and the resist pattern so that the ion travel direction forms a tilt angle with respect to an axis perpendicular to the top surface of the resist pattern. The method includes first rotating the structure and the resist pattern around the axis to a first position. The method includes first implanting ions into the resist pattern with the structure and the resist pattern at the first position.

Method for reducing line-end space in integrated circuit patterning

A semiconductor structure is provided. The semiconductor structure includes a gate structure over a substrate. The semiconductor structure also includes source/drain structures on opposite sides of the gate structure. The semiconductor structure also includes a dielectric layer over the gate structure and the source/drain structures. The semiconductor structure also includes a via plug passing through the dielectric layer and including a first group IV element. The dielectric layer includes a second group IV element, a first compound, and a second compound, and the second compound includes elements in the first compound and the first group IV element.

Semiconductor structure with doped via plug

A method includes forming a resist pattern, the resist pattern having trenches oriented lengthwise along a first direction and separated by resist walls along both the first direction and a second direction perpendicular to the first direction. The method further includes loading the resist pattern into an ion implanter so that a top surface of the resist pattern faces an ion travel direction, and tilting the resist pattern so that the ion travel direction forms a tilt angle with respect to an axis perpendicular to the top surface of the resist pattern. The method further includes rotating the resist pattern around the axis to a first position; implanting ions into the resist walls with the resist pattern at the first position; rotating the resist pattern around the axis by 180 degrees to a second position; and implanting ions into the resist walls with the resist pattern at the second position.

In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.

Process for making multi-gate transistors and resulting structures

A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure. The semiconductor structure also includes a source/drain structure in the fin structure and adjacent to the gate structure. The semiconductor structure also includes a first contact plug over the source/drain structure. The semiconductor structure also includes a first via plug over the first contact plug. The semiconductor structure also includes a dielectric layer surrounding the first via plug. The first via plug includes a first group IV element and the dielectric layer includes the first group IV element and a second group IV element.

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a source/drain structure, a first contact plug and a first via plug. The gate structure is positioned over a fin structure. The source/drain structure is positioned in the fin structure and adjacent to the gate structure. The first contact plug is positioned over the source/drain structure. The first via plug is positioned over the first contact plug. The first via plug includes a first group IV element.

Semiconductor structure with doped via plug and method for forming the same

A FinFET device structure and method for forming the same are provided. The method includes forming a fin structure over a substrate and forming a dummy gate electrode over a middle portion of the fin structure. The method also includes forming a spacer layer on the dummy gate electrode and on the fin structure and performing a plasma doping process on the dummy gate electrode and on the spacer layer. The method further includes performing an annealing process, wherein the annealing process is performed by using a gas comprising oxygen, such that a doped region is formed in a portion of the fin structure, and the spacer layer is doped with oxygen after the annealing process.

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Yuanshan, Taiwan

Jing-Huei Huang