United Microelectronics Corp.

United Semiconductor Corp.

Other

Jing-Horng Gau

Anchor Chen

Hsiu-Wen Huang

Shuenn-Jeng Chen

Jhy-Jyi Sze

Shu-Ya Chuang

A variable capacitor comprising a substrate having a first type ion-doped buried layer, a first type ion-doped well, a second type ion-doped region and a conductive layer thereon. The first type ion-doped well is formed within the substrate. The first type ion-doped well has a cavity. The first type ion-doped buried layer is in the substrate underneath the first type ion-doped well. The first type ion-doped buried layer and the first type ion-doped well are connected. The second type ion-doped region is at the bottom of the cavity of the first type ion-doped well. The conductive layer is above and in connection with the first type ion-doped buried layer.

Variable capactor structure and method of manufacture

A method of fabricating a capacitor is described. A dielectric layer is formed over a substrate. An upper electrode having multiple openings therein is formed over the dielectric layer. Then, a doping step is performed to the substrate through the openings to form a single doped region as a lower electrode in the substrate under the upper electrode.

Method of fabricating capacitor

A symmetrical inductor includes a first metal layer, the first metal layer having a first conductive segment disposed on a first side of a line, and a second conductive segment disposed on a second side of the line, the second conductive segment and the first conductive segment being symmetrical to the line; a second metal layer, the second metal layer having a third conductive segment disposed on the first side of the line, and a fourth conductive segment disposed on the second side of the line, the fourth conductive segment and the third conductive segment being symmetrical to the line; a first contact plug for connecting the first conductive segment with a first end of the third conductive segment; a second contact plug for connecting the first conductive segment with a second end of the third conductive segment; a third contact plug for connecting the second conductive segment with a first end of the fourth conductive segment, the third contact plug and the first contact plug being symmetrical to the line; and a fourth contact plug for connecting the second conductive segment with a second end of the fourth conductive segment, the fourth contact plug and the second contact plug being symmetrical to the line.

Symmetrical inductor

A metal-insulator-metal (MIM) capacitor includes a first metal plate; a first capacitor dielectric layer disposed on the first metal plate and a second metal plate stacked on the first capacitor dielectric layer. The first metal plate, the first capacitor dielectric layer, and the second metal plate constitute a lower capacitor. A second capacitor dielectric layer is disposed on the second metal plate. A third metal plate is stacked on the second capacitor dielectric layer. The second metal plate, the second capacitor dielectric layer, and the third metal plate constitute an upper capacitor. The first metal plate and the third metal plate are electrically connected to a first terminal of the MIM capacitor, while the second metal plate is electrically connected to a second terminal of the MIM capacitor.

Metal-insulator-metal (MIM) capacitor and fabrication method for making the same

A substrate with a plurality of isolation structures for defining at least an active area thereon is provided. Ions of a first conductive type are implanted into the substrate to form a doping region in the active area. Following that, a protective layer is formed on the substrate, the protective layer having an opening to expose the doping region. A first doping layer of a second conductive type and a second doping layer of the first conductive type are formed on the doping region, respectively, to complete fabrication of a bipolar junction transistor.

Method of fabricating a bipolar junction transistor

A method of forming a varactor includes forming an ion well of a first conductivity type on a substrate and a plurality of isolation structures on the ion well. The isolation structures define at least an active area on the ion well. Following that, ions of the first conductivity type are implanted into the ion well to form a doping region within the active area. A doping layer of a second conductivity type is then formed on the substrate to cover portions of the doping region. A salicide layer is formed on the doping region and the doping layer.

Method of forming a varactor

A varactor is provided. The varactor includes a second type substrate, two gate structures, a first type doped region and a second type doped region. The two gate structures are disposed over the substrate, and each of the gate structures includes an inter-gate dielectric layer and a gate conductive layer. The first type doped region is disposed in the substrate between the two gate structures. The second type doped region is disposed in the substrate at a side of the two gate structures apart from the first type doped region. The first type doped region is electrically connected to a first electrode, and second type doped region is electrically connected to a second electrode, and the two gate structures are electrically connected to the first electrode or the second electrode.

Varactor and differential varactor

A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed in an upper portion of the second doping region. A shielding layer is formed and a portion of the shielding layer is removed to form an opening shielding layer to expose a portion of the third doping region. Subsequently, a doping layer of the second conductivity type is formed on a surface of the third doping region. A self-aligned silicidation process is performed to form a silicide layer on the surfaces of the second doping region, the third doping region and the doping layer, the silicide layer functioning as a contact region of a vertical bipolar junction transistor.

Method for fabricating a vertical bipolar junction transistor

A method for fabricating a self-aligned bipolar transistor, wherein a substrate having an epitaxial layer formed thereon as a base is provided. After this, a first dielectric layer, a second dielectric layer are sequentially formed on the epitaxial layer, followed by forming an opening in the second dielectric layer. A conductive spacer is formed on the sidewall of the opening. Using the second dielectric layer and the conductive spacer as a mask, a first dielectric layer in the opening is removed. A conductive layer is then formed in the opening as an emitter, followed by completely removing the second dielectric layer. A doping is conducted on the emitter. Using the emitter and the conductive spacer as a mask, a part of the first dielectric layer is removed. Further using the emitter and the conductive spacer as a mask, another doping is conducted to form a part of the epitaxial layer as a base contact region.

Fabrication of self-aligned bipolar transistor

A PN-junction varactor includes a first ion well of first conductivity type formed on a semiconductor substrate of second conductivity type. A first dummy gate is formed over the first ion well. A first gate dielectric layer is formed between the first dummy gate and the first ion well. A second dummy gate is formed over the first ion well at one side of the first dummy gate. A second gate dielectric layer is formed between the second dummy gate and the first ion well. A first heavily doped region of the second conductivity type is located in the first ion well between the first dummy gate and the second dummy gate. The first heavily doped region of the second conductivity type serving as an anode of the PN-junction varactor. Second heavily doped regions of the first conductivity type located in the first ion well at one side of the first dummy gate that is opposite to the first heavily doped region and at one side of the second dummy gate that is opposite to the first heavily doped region, the second heavily doped regions being electrically connected to each other and serving as a cathode of the PN junction varactor.

Junction varactor with high Q factor and wide tuning range

An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.

Method of manufacturing anti-reflection layer

A structure of a DRAM and a manufacturing process therefor, suitable for a substrate on which a plurality of word lines and a plurality of source/drain regions on sides of each of these word lines are formed. A plurality of bit line contacts and a plurality of node contacts are formed in electric contact with the source/drain regions. A first patterned insulating layer is formed on the substrate, in which a plurality of openings are formed in the insulating layer to expose the bit line contacts. The substrate is covered with a first conductive layer and a second insulating layer in sequence. The second insulating layer, the first conductive layer and the first insulating layer are patterned in sequence to form a plurality of bit line stacked structures and a plurality of bit lines electrically connecting to the bit contacts, exposing the node contacts. As a result, the bit line stacked structure forms a plurality of trenches and the bit line stacked structure is orthogonal to the word lines. A plurality of spacers are formed on sidewalls of the bit line stacked structure. A plurality of second conductive layers are formed conformal to the surfaces of the trenches. The second conductive layers are patterned to form a plurality of bottom electrodes electrically connected to the node contacts.

Structure of a DRAM and a manufacturing process therefor

A self-aligned bit-line contact opening and node contact opening fabrication process having the following features: Etching of the periphery MOS spacer is performed before ion implantation of the periphery MOS source/drain region, using the same photoresist layer as a mask. A self-aligned bit-line (node) contact opening and a periphery gate contact opening, above the periphery MOS gate, are formed simultaneously. The etching of the memory cell MOS spacer is performed after the self-aligned bit-line (node) contact opening has been formed. At the same time, the cap layer above the periphery MOS gate, exposed by the periphery gate contact opening, is etched through.

Growing community of inventors

Hsinchu Hsien, Taiwan

Jing-Horng Gau