Taiwan Semiconductor Manufacturing Comp. Ltd.

Sky Tech Inc.

Micron Technology Incorporated

Other

Jing-Cheng Lin

Chen-Hua Douglas Yu

Po-Hao Tsai

Jui-Pin Hung

Szu-Wei Lu

Ying-Ching Shih

Cheng-Lin Huang

Shin-Puu Jeng

Li-Hui Cheng

Chih-Wei Wu

Szu Wei Lu

Wen-Chih Chiou

Chin-Chuan Chang

Shih Ting Lin

Nai-Wei Liu

Shang-Yun Hou

Jung-Hua Chang

Pu Wang

Der-Chyang Yeh

Chi-Hsi Wu

Yung-Chi Lin

Shau-Lin Shue

Feng-Cheng Hsu

Li-Chung Kuo

Hsien-Pin Hu

Chin-Fu Kao

Yi-Chao Mao

Long Hua Lee

Tsei-Chung Fu

Ku-Feng Yang

Fang Wen Tsai

An-Jhih Su

Weng-Jin Wu

Ching-Hua Hsieh

Chung Yu Wang

Hsin Chang

Hsien-Ju Tsou

Wan-Ting Shih

Yi-Hang Lin

Cheng-Chieh Hsieh

Hsin-Yu Chen

Kung-Chen Yeh

Ying-Da Wang

Ying Ching Shih

Tsan-Hua Tung

Mong-Song Liang

Shuo-Mao Chen

Hsien-Ming Lee

Shing-Chyang Pan

Chiung-Han Yeh

Yi-Jou Lin

Yu-Te Shen

Shih-Yi Syu

Kuo-Ching Hsu

Hsien-Wen Liu

Chao-Hsien Peng

Yi-Lin Tsai

Ta-Hao Kuo

Ming-Fa Chen

Kuan-Yu Huang

Yu-Liang Lin

Wen-Hsin Wei

Ming Shih Yeh

Yu-Wei Chen

Min-Chen Lin

Hung-Jui Kuo

Ming-Hsing Tsai

Tsang-Jiuh Wu

Chih-Hao Chen

Hung-Jung Tu

Shih-Ting Lin

Li-Lin Su

Yan-Fu Lin

Tsung-Fu Tsai

Li-Shyue Lai

Chih-Chien Pan

Kewei Zuo

Chen-Yu Tsai

Chien Rhone Wang

Chia-Ho Chen

Chun Hui Yu

Shih-Hui Wang

Yen-Hung Chen

Chia-Cheng Ku

Winston Shue

Chih-Chiang Chang

Hung-Wen Su

Wen-Chun Huang

Hsi-Kuei Cheng

Kuo-Chio Liu

Meng-Liang Lin

Chih-Hsien Lin

Hsiang-Tai Lu

Ting-Chu Ko

Chien-Chen Li

Shih-Wei Chou

Mong Song Liang

Chih-Wei Lai

Ruey-Yun Shiue

Chen-Hsuan Tsai

A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a concave upper surface facing the first ground bump.

Chip package structure with conductive shielding film

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

Semiconductor device having underfill surrounding bottom package and solder ball

A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

Through-substrate vias with improved connections

A method of manufacturing a semiconductor device includes following operations. A substrate is received. An electrical conductor is formed over a surface of the substrate. A photo-curable material is selectively dispensed over the surface of the substrate. The photo-curable material is irradiated to form a passivation layer is formed over the surface of the substrate. The passivation layer partially covers an edge of the electrical conductor.

Method of manufacturing semiconductor device including passivation layer

Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes coupling through-vias to an insulating material, each of the through-vias having a first width. Dies are also coupled to the insulating material. A portion of the insulating material is removed proximate each of the through-vias. The portion of the insulating material proximate each of the through-vias removed has a second width, the second width being less than the first width.

Methods of packaging semiconductor devices and packaged semiconductor devices

A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

Method for forming a semiconductor device including forming a first interconnect structure on one side of a substrate having first metal feature closer the substrate than second metal feature and forming first and second tsv on other side of substrate connecting to the metal features

A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

Method of manufacture overlay mark using laser marking process for semiconductor device

A semiconductor device and method utilizing a dummy structure in association with a redistribution layer is provided. By providing the dummy structure adjacent to the redistribution layer, damage to the redistribution layer may be reduced from a patterning of an overlying passivation layer, such as by laser drilling. By reducing or eliminating the damage caused by the patterning, a more effective bond to an overlying structure, such as a package, may be achieved.

Dummy structure of stacked and bonded semiconductor device

In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

Package structure and method

A package structure includes a first semiconductor package and a second semiconductor package over the first semiconductor package. The first semiconductor package includes a dielectric structure, a semiconductor device on the dielectric structure, under bump metallization (UBM) structures in the dielectric structure. The USB structures each include a first region and a second region surrounded by the first region. The first region has more metal layers than the second region. The bumps are respectively on the second regions of the UBM structures.

Package structure

A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chipsmay be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

Fan-out wafer level package structure

A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

Method of forming integrated fan-out packages with built-in heat sink

A method is provided that includes operations as follows: bonding an epitaxial layer formed with a first semiconductor substrate and an ion-implanted layer that is formed between the epitaxial layer and the first semiconductor substrate, to a bonding oxide layer of a second semiconductor substrate; separating the first semiconductor substrate from the epitaxial layer, by removing the first semiconductor substrate together with a portion of the ion-implanted layer and keeping the epitaxial layer; and forming a first semiconductor device portion on the epitaxial layer, and an interconnect layer on the first semiconductor device portion.

Bonded semiconductor structures

A parallelism-adjustable bonding machine includes a first chamber, a second chamber, a press-bonding unit, a carrier and plural parallelism-adjusting units. The first chamber is configured to connect to the second chamber, so as to define a closed space therebetween. The press-bonding unit is disposed within the first chamber, and the carrier is disposed within the second chamber. The press-bonding unit is disposed to face the carrier configured to press and bond substrates placed on the carrier. Each of the parallelism-adjusting units is disposed on the first chamber, and includes an adjustment shaft extending through the first chamber and connected to the press-bonding unit. The adjustment shaft includes an adjustment member located outside the first chamber and the closed space. A user is able to adjust a parallelism between the press-bonding unit and the carrier in an efficient and precise manner, from the adjustment member.

Parallelism-adjustable bonding machine

A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

Underfill structure for semiconductor packages and methods of forming the same

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Hsinchu, Taiwan

Jing-Cheng Lin