Western Digital Technologies, Inc.

Marvell International Limited

Jing Booth

Andrew John Tomlin

Mei-Man L Syu

Dmitry Obukhov

Kamyar Souri

Robert L Horn

Vincent M Wong

Jerry Lo

Stephen J Silva

Subhash Balakrishna Pillai

Jitendra Kumar Swarnkar

Chandra M Guda

Jie Du

Rebekah A Wilson

Justin Ha

Disclosed embodiments are directed to systems and methods for improving garbage collection and wear leveling performance in data storage systems. The embodiments can improve the efficiency of static wear leveling by picking the best candidate block for static wear leveling and/or postponing static wear leveling on certain candidate blocks. In one embodiment, one or more source blocks for a static wear leveling operation are selected based at least on whether the one or more blocks have a low P/E count and contain static data, such as data that has been garbage collected.

Systems and methods for improving garbage collection and wear leveling performance in data storage systems

Disclosed embodiments are directed to systems and methods for assigning and selecting memory units for internal memory operations in data storage systems. The embodiments can improve the efficiency of garbage collection operations by directing dynamic data into memory units with a relatively lower P/E count, directing static and system data into memory units with a relatively higher P/E count, and not mixing static and dynamic data by packing static data into separate memory units from dynamic data. In one embodiment, after completion of garbage collection of blocks, the blocks are each assigned to one of a cool down list and an available memory unit list based on a size limit of the cool down list and a number of program-erase (P/E) operations performed on each block. The blocks are subsequently selected from the lists for write operations according to whether write data includes static or dynamic data.

Memory unit assignment and selection for internal memory operations in data storage systems

An example device includes a memory device and one or more processors. The memory device is configured to store a table that includes two or more mappings, each mapping being associated with a respective logical address and a respective physical address. The processors are configured to identify, within the table, a first zone and a second zone. Each zone includes one or more mappings of the table. The zones do not share any mapping of the table. The processors are further configured to form a first log list indicating one or more mapping updates associated with the mapping(s) included in the first zone, to form a second log list indicating one or more mapping updates associated with the mapping(s) included in the second zone, and to replay a portion of the first log list and a portion of the second log list concurrently to update the table.

Zoning of logical to physical data address translation tables with parallelized log list replay

Embodiments of systems and methods that ensure integrity of data during unexpected power interruption of loss are disclosed. In some embodiments, critical data is saved quickly and efficiently using backup power. Data integrity is ensured even when the reliability of backup power sources is an issue. In some embodiments, by skipping the updating and saving of system data while operating on backup power, significant reduction of time for saving critical data can be achieved. System data can be restored next time the data storage system is restarted. Improvements of data storage system reliability are thereby attained.

Fast saving of data during power interruption in data storage systems

A data storage system configured to manage unreliable memory units is disclosed. In one embodiment, the data storage system maintains an unreliable memory unit list designating memory units in a non-volatile memory array as reliable or unreliable. The unreliable memory unit list facilitates management of unreliable memory at a granularity level finer than the granularity of a block of memory. The data storage system can add entries to the unreliable memory unit list as unreliable memory units are discovered. Further, the data storage system can continue to perform memory access operations directed to reliable memory units in blocks containing other memory units determined to be unreliable. As a result, the operational life of the data storage system is extended.

Managing unreliable memory in data storage systems

A disk drive is disclosed that utilizes multi-tiered solid state memory for caching data received from a host. Data can be stored in a memory tier that can provide the required performance at a low cost. For example, multi-level cell (MLC) memory can be used to store data that is frequently read but infrequently written. As another example, single-level cell (SLC) memory can be used to store data that is frequently written. Improved performance, reduced costs, and improved power consumption can thereby be attained.

Disk drive data caching using a multi-tiered memory

A data storage system configured to perform prioritized memory scanning for memory errors is disclosed. In one embodiment, the data storage system prioritizes scanning for memory errors based on a quality attribute of pages or zones of a non-volatile memory array. Pages or zones having quality attributes that reflect a lower level of reliability or endurance than other pages or zones are scanned more frequently for memory errors. When memory errors are discovered, the quality attribute of pages or zones can be adjusted to reflect a lower level of reliability or endurance. In addition, stored data can be recovered before it may become permanently lost and before a host system reads the stored data. Improved performance of the data storage system is thereby attained.

Prioritized memory scanning for data storage systems

Embodiments of the invention are directed to systems and methods for reducing the number of interrupts on a controller for a non-volatile storage device to improve data transfer performance of the storage system. The embodiments described herein selectively enable an interrupt generated by host transfer hardware for a host command. The interrupt can be enabled or disabled by considering the command type, availability of interface resources to accept additional host transfers, and the command size. Embodiments described herein are useful for host interfaces implementing a tagging scheme for host transfers with a limited range of identification tags.

Selectively enabling a host transfer interrupt

A system and method of buffer management may employ a common data structure that is recognizable by both hardware and firmware. In some implementations, hardware register settings may be programmed independent of firmware updates to an internal sub-segment description table maintained in an ASIC or other buffer manager logic. Implementation of such a common data structure in external memory may substantially reduce hardware real estate and complexity of a buffer manager ASIC by minimizing the number of required registers and eliminating the need for an internal sub-segment descriptor table. In addition, by eliminating the internal sub-segment descriptor table and allowing buffer manager logic to recognize a common data structure in external memory, the number of buffer sub-segments recognized by the buffer manager may be readily expanded, and may be limited only by the size of the external memory.

Unlimited sub-segment support in a buffer manager

A hard disk drive (HDD) controller comprises a channel module and a control module. The channel module reads and writes data to a magnetic medium. The control module defines non-overlapping first and second areas of the magnetic medium, receives a write request containing first data for a first address in the first area, and caches the first data at a second address in the second area before storing the first data at the first address.

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San Jose, CA, United States of America

Jing Booth