Everpro Technologies Comp Any Limited

Everpro (wuhan) Technologies Company Limited

Jinfeng Tian

Yan Li

Liang Xu

Yufeng Cheng

Hui Jiang

Xinliang Zhou

Ting Chen

Dezhen Li

Yanan Chen

An active cable supporting high-speed signal link training includes a first end, a second end, and a high-speed media signal line and a low-speed control signal line between the first end and the second end. The first end is configured for connecting a source end, the second end is configured for connecting a display end, the low-speed control signal line is configured for transmitting a low-speed sideband signal, the high-speed media signal line is configured for transmitting a high-speed media signal, and the second end is provided with, or the first end and the second end are respectively provided with a signal monitoring module connected with a signal line in the low-speed control signal line; and a high-speed signal adjusting module configured for receiving the link training data or the judgment result identified based on the link training data.

Active cable supporting high-speed signal link training

A USB active optical cable and a plug capable of managing power consumption and state. The USB active optical cable and plug respectively comprises a first plug, a second plug, and an optical transmission medium used to connect the first plug and the second plug; the first plug and the second plug are configured to operate different operating states, including an initialization mode, a transmission mode, and a power saving mode, and they can switch between the different operating states. The USB active optical cable and plug are both based on the separate control of the transmitting unit and the receiving unit to distinguish different operating modes, provide necessary operating requirements and mode switching conditions for each mode, and also enable the checking and transmission of the plugging state in the power saving mode, thus facilitate the power consumption management of the active optical cable.

USB active optical cable and plug capable of managing power consumption and status

A method of realization of adaptive equalization and an adaptive equalizer. The adaptive equalizer comprises an equalizer unit, which is used for equaling an input signal according to a compensation coefficient to obtain an output signal; a sampling comparison unit, which is connected to an output of the equalizer and is used for sampling a comparison result of the output signal of the equalizer and a reference voltage corresponding to reference voltage step; a data processing unit, which is connected to the sampling comparison unit and the equalizer unit. It is used for scanning a reference voltage step to determine range of the reference voltage steps to which step the amplitude of the output signal is corresponding; and scanning a compensation coefficient step, and determining the compensation coefficient for equalization according to the range of reference voltage steps. The solution of the present invention resolves such problems as long adaptive adjustment time, algorithm complex and large power consumption of the existing self-adaptive equalization algorithm.

Method of realization of adaptive equalization and adaptive equalizer

A method of frequency search and error correction of clock and data recovery circuit, comprising: initializing a frequency search algorithm parameter; processing a frequency error parameter UP/DN signals according to the set algorithm parameter and starting the frequency search, in which, the algorithm accordingly counts the UP/DN signals. When a phase error signal transition occurs, a transition parameter JUMP is accumulated by 1, and an accumulation parameter SUM is obtained and is further judged that whether a frequency search result is to be output. Number of repeating times of verification and threshold parameters are set, accordingly a reset DCRL value is obtained to verifies a frequency locking result and outputs the result. The present invention improves accuracy of UP/DN pulse counting, increases stability and reliability of the frequency locking, avoids a false locking in the frequency locking, and prevents an excessive locking time in the frequency locking, overcomes error judgment of the frequency search caused by a random jitter, and correctly completes the frequency search and locking, avoids failure of the CDR caused by an error frequency locking.

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Beijing, China

Jinfeng Tian