Samsung Electronics Co., Ltd.

Jinduck Park

Chansik Kwon

Jiyeon Han

Jongkeun Moon

Junyoung Ko

Yongseong Kim

Suyang Lee

Inwook Im

A semiconductor chip includes a semiconductor substrate including a device region, and an edge region surrounding the device region, a device layer on the semiconductor substrate, a wiring layer on the device layer, a side surface of the wiring layer at least partially defining a recessed region that is in the edge region such that the side surface of the wiring layer is exposed by the recessed region, and an upper insulating layer on the wiring layer. The recessed region extends from a side surface of the device layer toward the device region. A first portion of the upper insulating layer covers the side surface of the wiring layer that is exposed by the recessed region.

Semiconductor chips having recessed regions

Semiconductor packages may include a first semiconductor chip including a first through-electrode and a first upper connection pad and on an upper surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip and including a second lower connection pad on a lower surface of the second semiconductor chip, a connection bump between the first and second semiconductor chips and connected to the first upper connection pad and the second lower connection pad, a first insulating layer between the first and second semiconductor chips and surrounding the first upper connection pad, the connection bump, and the second lower connection pad, and a second insulating layer between the first semiconductor chip and the first insulating layer and extending on the upper surface of the first semiconductor chip, a side surface of the first upper connection pad, and a portion of a side surface of the connection bump.

Semiconductor packages

A test apparatus includes a test chamber in which a plurality of the semiconductor packages having a plurality of component dies is secured, an operation tester configured to conduct an operation test to the plurality of semiconductor packages to detect whether at least one semiconductor package is an operation fault package having a fault and identify a fault package point at which the operation fault package is located, a fault heat detector configured to detect a fault heat generated from the fault, and a test controller configured to control the operation tester to conduct the operation test to the plurality of semiconductor packages and control the fault heat detector subsequent to the operation test to detect the fault heat generated from the fault of the operation fault package to determine a vertical point of the fault and to determine a fault die having the fault.

Test apparatuses for testing semiconductor packages and manufacturing systems for manufacturing semiconductor packages having the same and methods of manufacturing the semiconductor packages using the same

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Asan-si, South Korea

Jinduck Park