Huawei Technologies Co., Limited

Jinda Yang

Liren Zhou

Qing Huang

Jun Xiong

A sampling clock generating circuit and an analog to digital converter (ADC) includes a variable resistance circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T, an output end of the NOT-gate type circuit is coupled to one end of the capacitor, the other end of the capacitor is grounded, a power supply terminal of the NOT-gate type circuit is connected to a power supply, a ground terminal of the NOT-gate type circuit is coupled to one end of the variable resistance circuit, and the other end of the variable resistance circuit is grounded, the NOT-gate type circuit is configured to output a low level when the pulse signal is a high level, and output a high level when the pulse signal is a low level.

Sampling clock generating circuit and analog to digital converter

A signal distribution circuit including an equalization circuit, a signal distribution part, an operational amplifying circuit, a feedback circuit, and a time sequence circuit. The equalization circuit is configured to collect an initial broadband signal. The signal distribution part is configured to distribute a first-stage broadband signal resulting from amplitude attenuation process to obtain a plurality of same second-stage broadband signals. The operational amplifying circuit is configured to perform amplification processing on the second-stage broadband signal obtained after distribution to obtain a third-stage broadband signal. The feedback circuit is configured to feedback the third-stage broadband signal to the equalization circuit. The time sequence circuit is configured to adjust an amplification gain of the third-stage broadband signal, and transmit the third-stage broadband signal to an analog to digital converter.

Signal distribution circuit and signal distribution circuit system

An ADC and an analog-to-digital conversion method are provided. The ADC includes: a clock generator, including M transmission gates, where the M transmission gates are configured to receive a first clock signal that is periodically sent and separately perform gating control on the first clock signal, so as to generate M second clock signals, M is an integer that is greater than or equal to 2; M ADC channels that are configured in a time interleaving manner, configured to receive one analog signal and separately perform, under the control of the M second clock signals, sampling and analog-to-digital conversion on the analog signal, so as to obtain M digital signals, where each ADC channel is corresponding to one clock signal of the M second clock signals; and an adder, configured to add the M digital signals together in a digital field, so as to obtain a digital output signal.

Analog-digital converter and analog-to-digital conversion method

A sampling clock generating circuit and an analog to digital converter includes a variable resistance circuit, and a NOT-gate type circuit, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the variable resistance circuit; and the other end of the variable resistance circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level.

A multi-channel clock distribution circuit and an electronic device includes a power source, a first switch, and at least two clock distribution sub-circuits; each clock distribution sub-circuit includes a second switch, a third switch, and a capacitor; a first end of the capacitor is connected to the power source by using the second switch and is connected to the first end of the first switch by using the third switch, a second end of the capacitor is grounded, and the first end of the capacitor is used as an output end of the clock distribution sub-circuits; and connection and disconnection of the first switch is controlled by a first clock signal, connection and disconnection of the second switch is controlled by a second clock signal, and connection and disconnection of the third switch is controlled by a third clock signal.

Multi-channel clock distribution circuit and electronic device

The present invention provides a level conversion circuit. The circuit is as follows: A cathode of a first equivalent diode is connected to a reference voltage, and an anode of the first equivalent diode is separately connected to a gate of a first switching transistor and a first end of a first capacitor; a second end of the first switching transistor and a first end of a second switching transistor are connected together; a second end of the second capacitor is separately connected to a cathode of a second equivalent diode and a gate of the second switching transistor; and a second end of the second switching transistor is grounded, and an anode of the second equivalent diode is connected to a reference voltage.

Level conversion circuit and apparatus

Embodiments of the present invention provide a comparator and an analog-to-digital converter. A sampling module, a pre-amplifying module, and a coupling module in the comparator obtain a third differential voltage signal according to a positive input signal and a negative reference signal, and obtain a fourth differential voltage signal according to a negative input signal and a positive reference signal. A latch that is in the comparator and formed by a first P-type field effect transistor, a second P-type field effect transistor, a third field effect transistor, a fourth field effect transistor, a first switch, and a second switch is directly cross-coupled through gates, and directly collects the third differential voltage signal and the fourth differential voltage signal to the gates, so as to drive the latch to start positive feedback.

Growing community of inventors

Shanghai, China

Jinda Yang