Samsung Electronics Co., Ltd.

Jinchan Ahn

Won-young Kim

Wonyoung Kim

Taeyoung Kim

Sanghyun Park

Chanho Lee

MuSeob Shin

Seokhong Kwon

Kyungseon Hwang

Hyunsoo Chung

Taewon Yoo

Myungkee Chung

Disclosed is a semiconductor package comprising a semiconductor chip and a redistribution layer. The semiconductor chip includes a semiconductor substrate, a passivation layer, and first power, second power, and signal pads exposed from the passivation layer. The redistribution layer includes a photosensitive dielectric layer, and first to third redistribution patterns and a high-k dielectric pattern that are in the photosensitive dielectric layer. The first, second, and third redistribution patterns are respectively connected to the first power, second power, and signal pads. The high-k dielectric pattern is between the first and second redistribution patterns. The photosensitive dielectric layer includes a first dielectric material. The high-k dielectric pattern includes a second dielectric material whose dielectric constant greater than that of the first dielectric material. The high-k dielectric pattern is in contact with the passivation layer. The passivation layer includes a dielectric material different from the first and second dielectric materials.

Semiconductor package

A semiconductor package includes a package substrate, at least one semiconductor chip mounted on the package substrate, a molding member on the package substrate to cover at least a portion of the semiconductor chip, and a mechanical reinforcing member provided around the semiconductor chip within the molding member and extending in at least one direction.

Semiconductor package and method of manufacturing semiconductor package

A semiconductor module includes a module substrate, a semiconductor package mounted on the module substrate, a first bonding wire connecting the module substrate to the semiconductor package, and a first molding member covering the first bonding wire. The semiconductor package includes a package substrate, a semiconductor chip mounted on the package substrate, a second bonding wire connecting the package substrate to the semiconductor chip, and a second molding member covering the semiconductor chip and the second bonding wire. The first and second bonding wires are each connected to one connection pad of the package substrate.

Semiconductor module including a semiconductor package connected to a module substrate and a bonding wire

Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

Semiconductor device having metal bump and method of manufacturing the same

A circuit board and a semiconductor packages therewith are disclosed. The circuit board may include a top surface, on which at least one semiconductor chip is mounted, and a bottom surface, to which at least one outer terminal is coupled. The top surface may include an upper window region, on which an upper conductive pattern electrically connected to the semiconductor chip is provided, and the bottom surface may include a lower window region, on which a lower conductive pattern electrically connected to the upper conductive pattern is provided. Here, a ratio of an area of the lower conductive pattern to an area of the upper conductive pattern may be less than or equal to 1.5.

Growing community of inventors

Hwaseong-si, South Korea

Jinchan Ahn