Infineon Technologies Ag

Intel Mobile Communications Gmbh

Jinan Lin

Xiaoning Nie

Lajos Gazsi

Lorenzo Di Gregorio

Soenke Mehrgardt

Tideya Kella

Siegmar Koeppe

Tilman Giese

Ralf Itjeshorst

Thomas Wahl

Sankamarayan Jagannathan

Xianming Deng

Denny Brem

Klaus Mott

Ulf Nordqvist

Sankar Narayan Jagannathan

Stefan Maier

A data moving processor includes a code memory coupled to a code fetch circuit and a decode circuit coupled to the code fetch circuit. An address stack is coupled to the decode circuit and configured to store address data. A general purpose stack is coupled to the decode circuit and configured to store other data. The data moving processor uses data from the general purpose stack to perform calculations. The data moving processor uses address data from the address stack to identify source and destination memory locations. The address data may be used to drive an address line of a memory during a read or write operation. The address stack and general purpose stack are separately controlled using bytecode.

Data moving processor

The invention relates to a device to be used with a thread scheduling method, and to a thread scheduling method comprising the steps of performing a scheduling for threads to be executed by a multithreaded (MT) processor (), characterized in that the scheduling is performed as a function of a variable (idle) representing the processor idle time.

Out-of-order thread scheduling based on processor idle time thresholds

A computing device includes a hardware data processing unit having at least one input buffer, a plurality of output buffers, a data transfer unit, and a software control unit, the data transfer unit configured to transfer data from the input buffer to the plurality of output buffers, and the software control unit configured to control the data transfer unit.

Data transfer in a computing device

In order to be able to use a smaller routing table () and, thus, to reduce the costs and power consumption and to improve the performance of an IP router, it is proposed to extract a destination address identifier (ADR) from a data packet to be forwarded by the IP router, compress the extracted destination address identifier (ADR) by using a lossless data compression algorithm, and compare the compressed destination address identifier with entries stored in the routing table () so as to find a correspondence between the destination address identifier and one of the entries of the routing table (). Each entry of the routing table () corresponds to a possible or available forwarding address of the IP router, the forwarding addresses having been compressed with the same data compression algorithm as the destination address identifier. After having found a correspondence between the destination address identifier and one of the compressed forwarding addresses stored in the routing table (), a switch () of the IP router switches the respective data packet to one of its output links (OUT) which is associated with the respective forwarding address matching the destination address identifier (ADR).

Method for routing of data packets and routing apparatus

An arrangement and a method for processing data of multiprotocol data packets comprises at least one multiplexer connected to input ports; at least one first programmable data processing unit configured to provide header words and into payload words; a buffer management unit configured to generate localization data which specifies a corresponding memory area of the payload memory; a descriptor generator unit for generating data packet descriptors; a RISC processor configured to generate, in dependence on the data packet descriptors, header data for transmit data packets and payload processing instructions for processing data of the data packet payload words, stored in the payload memory, of the associated received data packet; and at least one second programmable data processing unit configured to process the payload words from the payload memory in accordance with the payload processing instructions and assembles the payload words with the header data to form transmit data packets.

Multichannel processor

The present invention relates to a parallel multithread processor () with split contexts, with M parallel-connected standard processor root units () being provided for instruction execution of program instructions for different threads (T), and with N context memories () being provided, which each temporarily store a current state of a thread (T), and with a thread monitoring unit () being provided, by means of which each standard processor root unit () can be connected to each context memory (). The invention accordingly provides a processor architecture in which a number N of different context memories () and corresponding threads (T) are effectively fully networked with a number M of standard processor root units (). This means that use is made not only of paralleling of the standard processor root units (), but also of the threads (T) and of the context memories ().

Parallel multithread processor (PMT) with split contexts

In a method for forwarding data packets in a network a circuit comprises a data storage and a control device. Each data packet has a destination address and the data storage comprises T data sub-storages for storing all network addresses which are coded by a particular coding method on the basis of their respective key bit length in precisely one of the data sub-storages. The t-th data sub-storage is divided into blocks having D data elements of identical data element bit length, where t&#x3b5;[1, . . . , T] and D is the smallest common multiple of t&#x3b5;[1, . . . , T]. The control device receives data packets, each having a destination address, codes a destination address of a received data packet using the particular coding method to produce a coded key, and compares the coded key on the basis of its key bit length with the coded addresses stored in the corresponding data sub-store block by block in order to forward the respective data packet via an output to the destination address whose associated coded address matches the coded key from the respective received data packet.

Circuit and a method for forwarding data packets in a network

The invention relates to a heterogeneous parallel multithread processor () with shared contexts which has a plurality (M) of parallel-connected standard processor root unit types (; p&#x2208; [1, . . . , M]), where each respective standard processor root unit type () has at least one or more (K) parallel-connected standard processor root units (; q&#x2208; [1, . . . , K]) for instruction execution of program instructions from various threads (T), each standard processor root unit type () having N local context memories () which each buffer-store part of a current processor state for a thread. The multithread processor () also has a plurality (N) of global context memories (; t&#x2208; [1, . . . , N]) which each buffer-store part of a current processor state for a thread, and a thread control unit () which can connect any standard processor root unit () to any global context memory ().

Growing community of inventors

Ottobrunn, Germany

Jinan Lin