Samsung Electronics Co., Ltd.

Jinaeon Lee

Hyunsuk Kim

Yonggu Lee

Yongha Park

A method of processing multimedia data includes: separating a defined application kernel into a data patch kernel and a data processing kernel; requesting, by the data processing kernel, access to patch data of the multimedia data, from the data patch kernel; performing, by the data patch kernel, an operation that is independent of the request and preparing data for the data access based on the request; and performing, by the data processing kernel, an arithmetic operation on work items of the prepared data when the data has been prepared by the data patch kernel.

Multimedia data processing method in general purpose programmable computing device and data processing system according to the multimedia data processing method

An image processing apparatus and method of a camera is provided for compensating for shutter lag. An image processing apparatus includes an image scaler which scales a camera output image to a viewing image, a buffer which buffers the camera output image, a multiplexer which multiplexes outputs of the image scaler and the buffer, an image processor which processes multiplexed images corresponding to the multiplexed outputs of the image scaler and the buffer, a demultiplexer which demultiplexes an output of the image processor so as to supply the viewing image to a display unit, a codec which encodes the camera output image output by the demultiplexer into a capture image, and a controller which controls the multiplexer and the demultiplexer in a time divisional manner within a frame duration such that the image processor processes the viewing and camera output image sequentially in a capture mode.

Image processing apparatus and method of camera

The flash file system includes a flash memory and a subsystem interfacing between the flash memory and a host system. The subsystem includes a hierarchical structure of a host system interface, cache memory system, flash translation layer unit and a flash memory interface. The host system interface interfaces with the host system. The cache memory system has a storage capacity of a predetermined number of data units and stores data for transfer to and from the host system via the host system interface. The flash translation layer unit maps a logical address received from the host system via the host system interface and the cache memory into a physical address of the flash memory. The flash memory interface interfaces with the flash memory to transfer data to the flash memory from the cache memory system based on the physical address received from the flash translation layer unit and to transfer data from the flash memory to the cache memory system based on the physical address received from the flash translation layer unit.

Growing community of inventors

Suwon-si, South Korea

Jinaeon Lee