Texas Instruments Corporation

Jin Zhao

Nathan J Kruse

Jiong-Ping Lu

Manoj Mehrotra

Tae S Kim

Puneet Kohli

Sameer Kumar Ajmera

Ralf B Willecke

Yuqing Xu

August J Fischer

Ignacio Blanco

Linlin Chen

Manuel A Quevedo-Lopez

Qidu Jiang

Louis H Breaux

M Grant Albrecht

The present invention provides, in one embodiment, a process for cleaning a deposition chamber (). The process includes a step () of forming a reactive plasma cleaning zone by dissociating a gaseous fluorocompound introduced into a deposition chamber having an interior surface and in a presence of a plasma. The process () further includes a step () of ramping a flow rate of said gaseous fluorocompound to move the reactive plasma cleaning zone throughout the deposition chamber, thereby preventing a build-up of localized metal compound deposits on the interior surface. Other embodiments advantageously incorporate the process () into a system () for cleaning a deposition chamber () and a method of manufacturing semiconductor devices ().

Deposition tool cleaning process having a moving plasma zone

One embodiment of the present invention relates to a method of forming an isolation structure. During this method, an isolation trench is formed within a semiconductor body. After this trench is formed, it is filled by performing multiple high-frequency plasma depositions to deposit multiple dielectric layers over the semiconductor body. A first of the multiple layers is deposited at a high-frequency power of between approximately 100 watts and approximately 900 watts.

Method of forming an isolation structure by performing multiple high-density plasma depositions

The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.

Method for manufacturing an isolation structure using an energy beam treatment

The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.

Method for manufacturing a gate sidewall spacer using an energy beam treatment

A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a second layer of dielectric material adjacent the layer of silicon nitride.

Bi-layer etch stop process for defect reduction and via stress migration improvement

The present invention provides, in one embodiment, a method of manufacturing semiconductor devices. The method comprises transferring one or more substrate into a deposition chamber and depositing material layers on the substrate. The chamber has an interior surface. The method further includes, between the transfers, cleaning the deposition chamber using an in situ ramped cleaning process when material layer deposits in the deposition chamber reaches a predefined thickness. The in situ ramped cleaning process comprises forming a reactive plasma cleaning zone by dissociating a gaseous fluorocompound introduced into a deposition chamber in a presence of a plasma. The cleaning process further includes ramping a flow rate of the gaseous fluorocompound in a presence of the plasma to move the reactive plasma cleaning zone throughout the deposition chamber, thereby preventing a build-up of localized metal compound deposits on the interior surface.

Method of manufacturing semiconductor devices comprising a deposition tool cleaning process having a moving plasma zone

The present invention is directed to a method of forming a diffusion barrier layer for a FeRAM capacitor, which includes depositing a chemical vapor deposited titanium nitride layer in a via, and treating the chemical vapor deposited titanium nitride layer using a plasma treatment substantially excluding hydrogen.

Hydrogen-less CVD TiN process for FeRAM VIA0 barrier application

The present invention provides a system for preventing excess silicon consumption in a semiconductor wafer by depositing a metal layer ( ) on top of a native oxide layer above a silicide layer ( ) of the semiconductor wafer and then reducing the native oxide layer to form low resistance contacts. The native oxide layer is reduced using a rapid thermal annealing process within a temperature range to preserve the integrity of the silicide layer ( ) and reduce excess silicon consumption. The temperature range can be greater than 350&deg; C. and less than 615&deg; C., but is optimal between 485&deg; C. to 550&deg; C.

System for preventing excess silicon consumption in ultra shallow junctions

Disclosed is a system for fabricating a semiconductor device ( ). A layer of cobalt ( ) is deposited onto a silicon region ( ) and annealed to form a cobalt silicide layer ( ). Silicon layers ( ) are selectively deposited onto the cobalt silicide layers ( ). The semiconductor device ( ) is annealed to form disilicide layers ( ) from the cobalt silicide layers ( ) and the silicon contained in silicon regions ( ) and silicon layers ( ).

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Plano, TX, United States of America

Jin Zhao