Alibaba Group Holding Limited

Huazhong University of Science and Technology

Zhejiang Lab

China Jiliang University

Jin Zhao

Yu Zhang

Lin Wang

Wenchu Cen

Seshu Zheng

Yi Zeng

Hai Jin

Xiaofei Liao

Ting Jiang

Linlin Hou

Ting Yu

Wei Ye

Xiang Hui Zhao

Ji Zhang

Yicheng Chen

Dong Li

Yueping Liang

Zenghui Xu

Feng Guan

Tingjia Chen

Zhan Zhang

Hao Qi

Beibei Si

Haifei Wu

Shijun Li

Hui Yu

Xinyu Jiang

Yun Yang

The present invention relates to a post-exascale graph computing method, and corresponding system, storage medium and electronic device. The invention solves the problems of low computing performance, poor scalability and high communication overhead in the large-scale distributed environment, and improves the performance of the supercomputer when supporting large-scale graph computing.

Post-exascale graph computing method, system, storage medium and electronic device thereof

Disclosed in the present invention are a dynamic maximal clique enumeration device and method based on an FPGA with an HBM, the method including: the HBM stores a dynamic edge flow, a complete graph adjacency matrix, and candidate cliques; a matrix computing unit updates the complete graph adjacency matrix based on the dynamic edge flow, transmits the updated complete graph adjacency matrix to the HBM for storage, and determines header nodes, of which the corresponding candidate clique needs to be updated; a sequence computing unit constructs, according to the updated complete graph adjacency matrix and each header node to be updated, the sorted data set for reconstructing candidate cliques by data block sequencing; and an update computing unit executes, in parallel, an update task of the candidate clique corresponding to each header node to be updated based on the sorted data set, transmits the updated candidate cliques to the HBM for storage, and transmits the updated candidate cliques to the PC host to extract maximal cliques by means of a filtering operation. The present invention supports the computation of pipelined-type incremental maximal clique, thereby improving the overall computing efficiency of the task.

Dynamic maximal clique enumeration device and method based on FPGA with HBM

The present disclosure provides a data storage system, including data cache module, data processing module, and a persistent memory. The data cache module includes an on-chip mapping data cache and an on-chip counter cache, where the mapping data cache is configured to cache mapping data, and when the free space of the mapping data cache is less than a preset threshold, the least recently used mapping data cache line will be evicted from the cache and written back to the persistent memory. The data processing module encrypts/decrypts persistent memory data by using their counters, and accesses the persistent memory blocks indicated by their corresponding mapping data. The persistent memory comprises the first and second storage regions for the latest checkpoint data and modified working data in the current checkpoint interval respectively.

Data storing systems, data storing methods, and electronic devices

A data classification method and apparatus, a device and a storage medium. A structural feature of the respective node in graph data may be determined according to a neighbor node of the respective node in the graph data through a deviation between the decoded feature obtained by decoding the embedded coding feature of the respective node in the graph data and the initial feature of the respective node, and then the embedded coding feature corresponding to the respective node is adjusted according to the decoded feature of the respective node and the structural feature of the respective node in the graph data to obtain the adjusted feature corresponding to the respective node, so that accuracy of an obtained feature of the respective node is improved, and thus accuracy of data classification may be improved.

Data classification method and apparatus, device and storage medium

The present disclosure relates to an FPGA-based dynamic graph processing method, comprising: where graph mirrors of a dynamic graph that have successive timestamps define an increment therebetween, a pre-processing module dividing the graph mirror having the latter timestamp into at least one path unit in a manner that incremental computing for any vertex only depends on a preorder vertex of that vertex; an FPGA processing module storing at least two said path units into an on-chip memory directly linked to threads in a manner that every thread unit is able to process the path unit independently; the thread unit determining an increment value between the successive timestamps of the preorder vertex while updating a state value of the preorder vertex, and transferring the increment value to a succeeding vertex adjacent to the preorder vertex in a transfer direction determined by the path unit, so as to update the state value of the succeeding vertex.

FPGA-based dynamic graph processing method

The present invention provides a DNA barcode and method for identifying cuttlefishes, mainly depending on the diversity of mitochondrial DNA, including designing universal primers on conservative regions on both sides of the species-specific variable region, amplifying DNA from cuttlefishes, and sequencing PCR products to obtain DNA sequences, and identifying cuttlefish species based on the similarity by comparing with the species information in the database. The method is advantageous in that it can achieve efficient and specific amplification of DNA from such cephalopods as cuttlefishes, with low requirements for necessary instruments and simple operation processes. In addition, the method can be carried out in most molecular biology laboratories, which greatly improves the probability of success of molecular identification for cuttlefishes and sibling species thereof.

DNA barcoding primer for identifying cephalopoda and use thereof

A service integration platform system for providing Internet services includes: an interface configured to receive a service request message that is initiated by a user of an application provided by an Independent Software Vendor (ISV), the service request message being implemented according to an Application Programming Interface (API) type and including a plurality of platform-level parameters that conform to the API type. The system further includes one or more processors coupled to the interface, configured to: locate a set of authentication checks that are appropriate for the API type, based at least in part on the plurality of platform-level parameters included in the service request message and a mapping of predefined combinations of platform-level parameters and corresponding sets of authentication checks; perform authentication of the service request according to the set of authentication checks; and route the service request to a service address of the Internet Service Provider (ISP) in the event that the service request is authenticated.

Method and system for providing internet services

A service integration platform system includes an interface configured to receive a service request initiated by an Independent Software Vendor (ISV) and one or more processors configured to authenticate the service request and in the event that the service request is authenticated, route the service request to an Internet Service Provider (ISP) providing the service to be further processed. The service request is routed to a deployment environment provided by the ISP in the event that the service request is received on a deployment Universal Resource Identifier (URI) corresponding to the deployment environment; the service request is routed to a test environment provided by the ISP in the event that the service request is received on a test URI corresponding to the test environment.

Service integration platform system and method for internet services

Growing community of inventors

Hangzhou, China

Jin Zhao