Shanghai Zhaoxin Semiconductor Co., Ltd.

Via Alliance Semiconductor Co., Ltd.

Jin Yu

Fangfang Wu

Xiaoyang Li

Zongpu Qi

Lei Meng

Zheng Wang

Wei Zhao

Shican Luo

Lin Li

Kuan-Jui Ho

Mengchen Yang

Di Hu

Xuehua Han

A processing system includes at least one core, at least one accelerator function unit (AFU) and an acceleration interface. The unit runs a plurality of processes and develops at least one task queue corresponding to each of the processes. The core generates several command packets and pushes them into the corresponding task queue. The AFU are used to execute the command packets. The acceleration interface is arranged between the AFU and the core to receive an acceleration interface instruction from the processing core, and establish a bit map based on the acceleration interface instruction. The bit map is used to indicate which task queue contains the command packets that have been generated.

Processing system for managing process and its acceleration method

A processing system includes a cache, a host memory, a CPU and a hardware accelerator. The CPU accesses the cache and the host memory and generates at least one instruction. The hardware accelerator operates in a non-temporal access mode or a temporal access mode according to the access behavior of the instruction. The hardware accelerator accesses the host memory through an accelerator interface when the hardware accelerator operates in the non-temporal access mode, and accesses the cache through the accelerator interface when the hardware accelerator operates in the temporal access mode.

Hardware accelerators and access methods thereof

A processing system includes at least one core, several accelerator function units (AFU) and a microcontroller. The core is utilized to operate several processes and develop at least one task queue corresponding to each of the processes. The processing core generates several command packets and pushes them into the corresponding task queue. The AFU executes the command packets. The microcontroller is arranged between the AFU and the core to dispatch the command packet to a corresponding AFU for execution. When the corresponding AFU executes the command packet of a specific process of the processes, the microcontroller assigns the corresponding AFU to execute other command packets in the task queue of the specific process at a higher priority.

Processing system for scheduling and distributing tasks and its acceleration method

The invention introduces a method for accelerating compression, performed by configuration logic of a compression accelerator, containing: obtaining an input parameter from a processor core; obtaining a configuration setting from a compression parameter table according to the input parameter; configuring hardware coupled between a first buffer and a second buffer to form a data transmission path according to the input parameter, wherein the first buffer stores raw data; and transmitting the configuration setting to devices on the data transmission path for processing the raw data to generate compressed data and storing the compressed data in the second buffer.

Methods for accelerating compression and apparatuses using the same

The invention introduces a method for accelerating compression, performed in a compression accelerator, including: repeatedly executing a loop for determining the longest matched-length between a first string and a second string. Each iteration of the loop includes: obtaining n successive characters from the first string as a source string, wherein n is greater than 1; comparing each character of the source string with all characters of the second string, so as to generate n first-match-results corresponding to the n successive characters of the source string respectively; generating a second-match-result according to the n first-match-results; and determining whether a continuous match of the n successive characters is presented according to the second-match-result. If so, n is added to the matched length and the next iteration of the loop is continued to execute. Otherwise, a matched length is updated and output and the loop is exited.

Methods for accelerating hash-based compression and apparatuses using the same

The invention introduces a method for accelerating hash-based compression, performed in a compression accelerator, comprising: fetching a string to be compressed from a data buffer; storing instances corresponding to the string in an intermediary buffer; issuing a hash request to a hash matcher for each instance, issuing a data request to an LSM (longest string matcher) according to a first reply sent by the hash matcher, and updating a state, a match length and a match offset of the instance according to a second reply sent by the LSM; and outputting the result to a formatter according to the state, the match length and the match offset of each instance in the original order of the associated substrings that appeared in the string.

The invention introduces a method for accelerating hash-based compression, performed in a compression accelerator, comprising: receiving, by a plurality of hash functions, a plurality of substrings from an FSM (Finite-State Machine) in parallel; mapping, by each hash function, the received substring to a hash index and directing a selector to connect to one of a plurality of match paths according to the hash index; transmitting, by a matcher of each connected match path, a no-match message to the FSM when determining that a hash table does not contain the received substring; and transmitting, by the matcher of each connected match path, a match message and a match offset of the hash table to the FSM when determining that the hash table contains the received substring, wherein the match offset corresponds to the received substring.

Growing community of inventors

Shanghai, China

Jin Yu