Skhynix Inc.

Jin Youp Cha

Jae Il Kim

Soo Young Jang

Seung Hun Lee

Jae Jin Lee

Sang Sic Yoon

Hyun Seung Kim

Jin Hee Cho

Seung Wook Oh

Jeong Tae Hwang

Yu Ri Lim

Cheol Hoe Kim

Seok Cheol Yoon

Young Sik Heo

A semiconductor apparatus includes a transmission device and a receiving device. The transmission device generates an output signal from a transmission signal in synchronization with a clock signal. The receiving device generates a reception signal from the output signal in synchronization with the clock signal and a delayed clock signal generated by delaying the clock signal by a preset time, based on an operating speed of the semiconductor apparatus.

Semiconductor apparatus for transmitting and receiving a signal in synchronization with a clock signal

A system may include a first semiconductor apparatus and a second semiconductor apparatus. Each of the first and second semiconductor apparatuses may receive reference data and a first clock signal. The first semiconductor apparatus may generate a first internal clock signal from the first clock signal, and may output the reference data as transmission data based on the first internal clock signal. The second semiconductor apparatus may generate a second internal clock signal from the first clock signal, and may receive the transmission data based on the second internal clock signal. The second semiconductor apparatus may generate an error detection signal based on the received data and the reference data.

Semiconductor apparatus and system relating to performing a high speed test in a low speed operation environment

An error detection circuit may include a selection unit that sequentially selects a primary data group and a secondary data group according to a first control signal and generates an output signal; a first operation unit that performs an error detection operation on the output signal and outputs a preliminary error operation signal; a storage unit that latches the preliminary error operation signal and output a latched signal according to a second control signal; a second operation unit that performs an error detection operation on a previous preliminary error operation signal outputted from the storage unit and a current preliminary error operation signal outputted from the first operation unit and generates an internal error operation signal; and a comparison unit that compares the internal error operation signal with an external error operation signal and outputs a result of the comparison as an error detection signal.

Error detection circuit and semiconductor apparatus using the same

A memory apparatus may include a plurality of ranks commonly coupled to an input/output (I/O) terminal. Non-target ranks other than a target rank among the plurality of ranks may be configured to perform an on die termination operation based on a read operation of the target rank.

Memory apparatus relating to on die termination

A semiconductor integrated circuit device may include a target PMOS transistor, a target NMOS transistor, a first stress-applying circuit, a second stress-applying circuit, a third stress-applying circuit and a fourth stress-applying circuit. An inverter may include the target PMOS transistor and the NMOS transistor. The first stress-applying circuit may be configured to apply a first DC level to a gate of the target PMOS transistor. The second stress-applying circuit may be configured to apply a second DC level to a gate of the target NMOS transistor. The third stress-applying circuit may be configured to apply an AC voltage shape to the gate of the target NMOS transistor. The fourth stress-applying circuit may be configured to apply the AC voltage to a drain of the target NMOS transistor.

Semiconductor integrated circuit device regarding the detection of degradation

A semiconductor device may include a data output circuit configured to sense and amplify data of an input/output line and a complementary input/output line based on the sense amplification control signal. The semiconductor device may include a data output control circuit configured to delay a point of time that the input/output line and the complementary input/output line are sensed and amplified.

Semiconductor device and semiconductor system

A semiconductor apparatus includes a memory region configured to store data transmitted through a first data line and a second data line; and a precharge block configured to precharge the second data line to a level of a first voltage and precharge the first data line to a level of a second voltage higher than the level of the first voltage, based on a write signal.

Precharge circuit and semiconductor apparatus including the same

A column select signal generation circuit includes: a first current controller configured to control the level of a pre-column select signal in response to a bank active signal, a driver configured to generate an amplified column select signal in response to the pre-column select signal, and a second current controller configured to generate an output signal of the driver as a column select signal in response to the bank active signal.

Column select signal generation circuit

A semiconductor memory apparatus includes a data alignment control signal generation unit configured to output a data alignment control signal by generating a pulse when a tuning mode signal is enabled, and generate the data alignment control signal as a count pulse is inputted after the data alignment control signal generated by the tuning mode signal is outputted; a timing control block configured to determine a delay amount according to delay codes, generate a delay control signal by delaying the data alignment control signal, and output a timing control signal by latching the delay control signal at an enable timing of a data output control signal; a delay time control block configured to generate the delay codes; and a data alignment unit configured to convert parallel data into serial data, and change a data sequence of the serial data in response to the timing control signal.

Semiconductor memory apparatus

A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.

Test circuit and method of semiconductor memory apparatus

A data output circuit according to one embodiment of the present invention includes: a delay control block configured to generate a clock delay signal in response to a power-up signal and a reset signal; a first delay block configured to correct a duty ratio of a rising clock according to the clock delay signal and output the corrected rising clock; and a second delay block configured to correct a duty ratio of a falling clock according to the clock delay signal and output the corrected falling clock.

Data output circuit

An anti-fuse circuit includes: an anti-fuse unit including an anti-fuse capable of being programmed in response to a rupture signal and configured to generate a fuse signal corresponding to a state of the anti-fuse; a dummy fuse unit including a dummy fuse and configured to generate a dummy fuse signal corresponding to a state of the dummy fuse; and a blocking unit configured to output the fuse signal as a fuse output signal in response to a state of the dummy fuse signal.

Anti-fuse circuit

An anti-fuse circuit includes: a rupture unit including an anti-fuse programmed in response to an input rupture signal during a program mode, and configured to generate an output rupture signal corresponding to a state of the anti-fuse to output the generated output rupture signal to a transmission node, a voltage clamp unit configured to generate a clamp voltage proportional to an external voltage level to generate the clamp voltage having a constant voltage level when the external voltage level rises to a predetermined level or more, and a fuse signal generation unit configured to reset the transmission node to the clamp voltage at the initial stage of the program mode to generate a fuse signal in response to the voltage level of the transmission node during an output mode.

A fuse circuit includes a plurality of fuse sets configured to perform fuse programming and generate fuse signals in response to fuse programming signals and a fuse control unit configured to generate the fuse programming signals depending upon a level of a programming voltage.

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Icheon-si, South Korea

Jin Youp Cha