Hynix Semiconductor Inc.

Skhynix Inc.

Jin Yong Seong

Sam Kyu Won

Seong Jin Park

Jae Won Cha

Kyu Tae Park

Wan Seob Lee

Jun Sang Lee

Sang Bin Park

Gun Gi Song

Ho Jun Kang

Young Sang Ahn

Provided herein may be a storage device and a method of operating the storage device. A memory device may include a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform an operation on memory cells selected from among the plurality of memory cells, a voltage variation detector configured to generate voltage variation information indicating whether a voltage variation has occurred in a supply voltage during performance of the operation, a power register configured to store the voltage variation information, a status register configured to store status information indicating an operating status of the memory device, and a register output controller configured to update the status information provided from the status register based on the voltage variation information.

Storage device and method of operating of the storage device

A memory device having an improved booting speed includes: a memory cell array, and a control logic configured to set a memory block as one of a special block for storing special information and a user block for storing user data and configured to store data in a memory block in response to commands from a memory controller, wherein the control logic comprises: a control signal generator configured to generate a special information read signal for reading plural pieces of special information stored in at least two special blocks among the plurality of memory blocks, in response to a special information read command provided by the memory controller, a special information merger configured to read the plural pieces of special information in response to the special information read signal, and a special information storage configured to store the read plural pieces of special information as merged special information.

Storage device and operating method thereof

In a storage device having an improved data receiving rate, the storage device includes: a plurality of memory devices each including a plurality of select signal pads; and a memory controller for providing a plurality of select signals representing a selected memory device among the plurality of memory devices through the plurality of select signal pads, wherein some select signals among the plurality of select signals include stack information indicating a number of the plurality of memory devices controlled by the memory controller.

A semiconductor device may include: an internal voltage supplier, and a voltage level controller. The internal voltage supplier may supply an internal power supply voltage to be used for the operation of the semiconductor device. The voltage level controller may determine whether a voltage level change condition of the semiconductor device is satisfied and controls the internal voltage supplier to change a voltage level of the internal power supply voltage based on a result of the determining.

Semiconductor memory device, method of operating the same, and memory system

Provided herein may be a memory chip, a package device having the memory chip, and a method of operating the package device. The memory chip comprising a plurality of memory blocks each including a plurality of memory cells for storing data; a plurality of input/output pads to which a chip address is inputted; and a plurality of peripheral circuits configured to program the chip address to a selected memory block among the memory blocks.

Memory chip, package device having the memory chips, and operating method of package device

A semiconductor memory device includes a memory cell array, a status signal generator, an RB output control unit and a control logic. The memory cell array includes a plurality of memory cells. The status signal generator outputs an internal status signal indicating whether the memory cell array is performing an internal operation. The RB output control unit outputs a ready/busy signal based on the internal status signal. The control logic controls the RB output control unit to adjust an output current of the RB output control unit.

Semiconductor memory device with a control logic capable of controlling the ready busy output control unit to adjust an output current to be outputted to a ready/busy pad, and a method for operating the same

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a status signal generator configured to output an internal status signal indicating whether an operation of the memory cell array has been completed or is being performed and a ready/busy line input mode control unit configured to output a ready/busy signal through a ready/busy line based on the internal status signal or to receive an input signal from an external device through the ready/busy line.

Semiconductor memory device and method of operating the same

A semiconductor apparatus may include a unit chip and a characteristic measurement circuit configured to include a plurality of unit elements for test and to output electrical characteristic information of the plurality of unit elements for test.

Semiconductor apparatus and characteristic measurement circuit therefor

Provided herein may be a memory system and a method of operating the same. A semiconductor memory device may include a write protect pin mode setting unit configured to set, depending on a parameter value stored therein, a write protect pin of the semiconductor memory device as any one of an input pin and an output pin and a control logic configured to output, when the write protect pin serves as the output pin, internal state information of the semiconductor memory device to an external device.

Memory system and method for operating the same

A semiconductor device includes a data output circuit suitable for transferring an output data to an external data line during a data output operation, and a controller suitable for generating control signals for controlling the data output circuit during the data output operation, wherein the data output circuit senses a variation and transfers the output data to the external data line based on the sensing result.

Semiconductor device

A semiconductor device employs a technology for improving data retention characteristics of a cell array storing data regarding conditions for controlling internal operations of the semiconductor device. The semiconductor device includes a content addressable memory (CAM) cell array configured to store CAM data regarding conditions for controlling the internal operations, a control logic configured to store the CAM data read out of the CAM cell array, and a microprocessor configured to perform a reprogramming operation on the CAM cell array using the CAM data stored in the control logic.

Semiconductor device and method for operating the same

A multi-chip package includes a single lead and a plurality of inner package chips. Each of the plurality of inner package chips includes at least one pad circuit and an internal circuit. The pad circuit is selectively coupled to the lead and configured to provide a chip address signal corresponding to a connection state to the lead. The inner package chip receives the chip address signal to identify a corresponding inner package chip.

Multi-chip package

A semiconductor memory device includes memory blocks each including a plurality of groups of memory cells programmable in multiple levels and a control circuit configured to make a determination of whether a specific memory block treated a bad block, from among the memory blocks, is programmable in a single level and to control the specific memory block according to a result of the determination so that the specific memory block is usable as a single level cell block.

A multi-chip package according to an aspect of this disclosure includes a plurality of multi-chips. Each of the multi-chips includes a lead configured to receive an external power supply voltage, and a pad circuit configured to reset an internal node to the level of a ground voltage and to generate chip address information by controlling the potential of the internal node based on the state of a connection between the pad circuit and the lead.

Multi-chip package including chip address circuit

A memory chip includes a memory circuit unit configured to include memory cells for storing data, a data input and output (I/O) buffer unit configured to include a plurality of data I/O buffer circuits, wherein one of the data I/O buffer circuits is operated by default in order to input and output data to and from the memory chip, a plurality of driver control units configured to generate a plurality of driver addition signals to enable corresponding ones of the data I/O buffer circuits depending on whether a power supply voltage has been received, and a controller configured to generate I/O enable signals for controlling an operation of the data I/O buffer unit.

Growing community of inventors

Seoul, South Korea

Jin Yong Seong