Yangtze Memory Technologies Co., Ltd.

Jin Yong Oh

Youn Cheul Kim

Xiaojiang Guo

Yu Wang

Ye Tian

Siyuan Wang

Zhichao Du

ZhiChao Du

A method for operating a three-dimensional (3D) memory device includes performing a first read operation for sensing a first memory cell of a first transistor string, and performing a subsequent second read operation for sensing a second memory cell of a second transistor string. Performing the first read operation includes applying a first bit line voltage to a first bit line, and maintaining the first bit line basically undischarged after data state of the first memory cell is detected.

Three-dimensional memory device and improved methods of reading the same by shortening read times

A memory device includes a first semiconductor structure and a second semiconductor structure. The memory device further includes a bonding structure between the first semiconductor structure and the second semiconductor structure, the bonding structure comprising a first bonding pattern and a second bonding pattern in contact with each other, the first semiconductor structure being electrically connected with the second semiconductor structure through the bonding structure. The memory device further includes a shielding structure between the first semiconductor structure and the second semiconductor structure and surrounding the bonding structure, the shielding structure comprising a third bonding pattern and a fourth bonding pattern in contact with each other, the shielding structure being electrically connected with a biased voltage.

Non-volatile memory device and manufacturing method thereof

A non-volatile memory device includes a substrate, a plurality of memory blocks grouped into pages, each including an alternating layer stack on the substrate, a plurality of channel holes in the alternating layer stack, and strings of memory cells disposed along the plurality of channel holes, and at least one dummy block adjacent to the plurality of memory blocks, each including an alternating dummy layer stack having multiple conductive layers and multiple dielectric layers alternately laminated on one another on the substrate, the at least one dummy block is disposed at an outskirt of each of the pages of the plurality of memory blocks.

Non-volatile memory device utilizing dummy memory block as pool capacitor

A semiconductor device includes a first substrate having a first side for forming memory cells and an opposing second side, a doped region formed in the first side of the first substrate, a first connection structure formed over the second side of the first substrate and coupled to the doped region through a first VIA, and a transistor formed in a first side of a second substrate and coupled to the first connection structure. The first VIA extends from the second side of the first substrate to the doped region. The memory cells include a plurality of word lines formed over the first side of the first substrate, a plurality of insulating layers disposed between the plurality of word lines, and a common source structure coupled to and extending from the doped region, and further extending through the plurality of word lines and the plurality of the insulating layers.

3D NAND memory device and method of forming the same

Read time of three-dimensional memory device

A memory device includes a memory array, a circuit structure, a bonding structure between the memory array and the circuit structure, and a shielding structure between the memory array and the circuit structure and surrounding the bonding structure. The bonding structure includes a first bonding pattern and a second bonding pattern. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure includes a third bonding pattern and a fourth bonding pattern. The first bonding pattern is in contact with the second bonding pattern at a first interface between the first bonding pattern and the second bonding pattern. The third bonding pattern is in contact with the fourth bonding pattern at a second interface between the third bonding pattern and the fourth bonding pattern.

A 3D-NAND memory includes a transistor formed in a first side of a periphery circuit substrate, a memory cell stack formed over a first side of a cell array substrate, and a first connection structure formed over an opposing second side of the cell array substrate. The memory cell stack includes a doped region formed in the first side of the cell array substrate and coupled to the first connection structure through a first VIA, a common source structure that extends from the doped region toward the first side of the periphery circuit substrate, and a second connection structure that is positioned over and coupled to the common source structure. The first side of the cell array substrate and the first side of the periphery circuit substrate are aligned facing each other so that the transistor is coupled to the second connection structure.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a first insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the first insulating structure. The 3D memory device further includes a first contact extending vertically from the second side of the substrate to be in contact with the first doped region.

Three-dimensional memory devices and methods for forming the same

Memory device and formation method are provided. The memory device includes a substrate; a staircase structure on the substrate; a string driver structure over the staircase structure on a side opposite to the substrate; and a metal routing structure, between the string driver structure and the staircase structure along a vertical direction with respect to a lateral surface of the substrate. The staircase structure includes a plurality of word line tiers. The string driver structure includes a plurality of transistors to individually address the plurality of word line tiers. The string driver structure and the metal routing structure are vertically aligned with the staircase structure based on a lateral central region of the staircase structure.

Memory device having staircase structure including word line tiers and formation method thereof

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a slit structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the slit structure. The 3D memory device further includes an insulating structure extending vertically from the second side of the substrate to the first doped region. The 3D memory device further includes a plurality of second doped regions in the substrate and separated by the insulating structure.

Three-dimensional memory devices having a backside trench isolation and methods for forming the same

A non-volatile memory device includes a plurality of memory blocks and a dummy block configured to form a pool capacitor for suppressing power noise. The dummy block includes a substrate, a conductor region in the substrate, and an alternating dummy layer stack on the conductor region. The alternating dummy layer stack includes multiple conductive layers and multiple dielectric layers alternately laminated on one another.

A semiconductor device is provided. The semiconductor device includes a first substrate that has a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device also includes a doped region and a first connection structure. The doped region is formed in the first side of the first substrate and is electrically coupled to at least a source terminal of a transistor (e.g., a source terminal of an end transistor of multiple transistors that are connected in series). The first connection structure is formed over the second side of the first substrate and coupled to the doped region through a first VIA. The first VIA extends from the second side of the first substrate to the doped region.

A non-volatile memory device includes a first substrate, a second substrate, a memory array, a circuit structure, a bonding structure, and a shielding structure. A second front side of the second substrate faces a first front side of the first substrate. The memory array is disposed on the first substrate and disposed at the first front side of the first substrate. The circuit structure is disposed on the second substrate and disposed at the second front side of the second substrate. The bonding structure is disposed between the memory array and the circuit structure. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure is disposed between the memory array and the circuit structure and surrounds the bonding structure. The shielding structure is electrically connected to a voltage source.

A non-volatile memory device includes a plurality of memory blocks grouped into pages, page buffer regions corresponding to the pages of the plurality of memory blocks; and a peripheral circuit region for supporting operations of the pages of the plurality of memory blocks. The peripheral circuit region comprises a plurality of pool capacitors. At least one of the memory blocks is a dummy block. The dummy block is configured to form a supplementary pool capacitor for suppressing power noise.

Growing community of inventors

Wuhan, China

Jin Yong Oh