Electronics and Telecommunications Research Institute

Jin Yeong Kang

Sang Heung Lee

Seung Yun Lee

Kyu Hwan Shim

Kyoung Ik Cho

Sang Hoon Kim

Bo Woo Kim

Yong Sun Yoon

Young Joo Song

Jin Gun Koo

Kun Sik Park

Jong Moon Park

Jae Seung Lee

Jin Ho Lee

Sang Hun Kim

Ja Yol Lee

Chong Ki Kwon

Bong Ki Mheen

Min Hyung Cho

Seong Wook Yoo

Hyun Cheol Bae

Jeon Wook Yang

Hyeon Cheol Ki

Kyong Ik Cho

Young K Choe

Seung Hyeub Oh

Disclosed is a CMOS image sensor and a manufacturing method thereof. According to an aspect of the present invention, each pixel of CMOS image sensor includes a photo detector that includes an electon Collection layer doped with a concentration of 5&#xd7;10/cmto 2&#xd7;10/cm; and a transfer transistor that is connected to the photo detector and is formed of a vertical type trench gate of which the equivalent oxide thickness is 120 &#x212b; or more.

CMOS image sensor

A complementary metal-oxide semiconductor (CMOS)-based planar type avalanche photo diode (APD) using a silicon epitaxial layer and a method of manufacturing the APD, the photo diode including: a substrate; a well layer of a first conductivity type formed in the substrate; an avalanche embedded junction formed in the well layer of the first conductivity type by low energy ion implantation; the silicon epitaxial layer formed in the avalanche embedded junction; a doping area of a second conductivity type opposite to the first conductive type, formed from a portion of a surface of the well layer of the first conductivity type in the avalanche embedded junction and forming a p-n junction; positive and negative electrodes formed on the doping area of the second conductivity type and the well layer of the first conductivity type separated from the doping area of the second conductivity type, respectively; and an oxide layer formed on an overall surface excluding a window where the positive and negative electrodes are formed.

CMOS-based planar type silicon avalanche photo diode using silicon epitaxial layer and method of manufacturing the same

Provided are an NMOS device, a PMOS device and a SiGe HBT device which are implemented on an SOI substrate and a method of fabricating the same. In manufacturing a Si-based high speed device, a SiGe HBT and a CMOS are mounted on a single SOI substrate. In particular, a source and a drain of the CMOS are formed of SiGe and metal, and thus leakage current is prevented and low power consumption is achieved. Also, heat generation in a chip is suppressed, and a wide operation range may be obtained even at a low voltage.

NMOS device, PMOS device, and SiGe HBT device formed on SOI substrate and method of fabricating the same

Provided is an image sensor having a heterojunction bipolar transistor (HBT) and a method of fabricating the same. The image sensor is fabricated by SiGe BiCMOS technology. In the image sensor, a PD employs a floating-base-type SiGe HBT. A floating base of the SiGe HBT produces a positive voltage with respect to a collector during an exposure process, and the HBT performs a reverse bipolar operation due to the positive voltage so that the collector and an emitter exchange functions. The SiGe HBT can sense an optical current signal and also amplify the optical current signal. The image sensor requires only three transistors in a pixel so that the degree of integration can increase. The image sensor has an improved sensitivity of signals in the short wavelength region and a sensing signal has excellent linearity such that both a sensing mechanism and control circuit are very simple.

Image sensor having heterojunction bipolar transistor and method of fabricating the same

A BJT (bipolar junction transistor)-based uncooled IR sensor and a manufacturing method thereof are provided. The BJT-based uncooled IR sensor includes: a substrate; at least one BJT which is formed to be floated apart from the substrate; and a heat absorption layer which is formed on an upper surface of the at least one BJT, wherein the BJT changes an output value according heat absorbed through the heat absorption layer. Accordingly, it is possible to provide a BJT-based uncooled IR sensor capable of being implemented through a CMOS compatible process and obtaining more excellent temperature change detection characteristics.

Bipolar junction transistor-based uncooled infrared sensor and manufacturing method thereof

Provided are a high-quality CMOS image sensor and a photo diode, which can be fabricated in sub-90 nm regime using nanoscale CMOS technology. The photo diode includes: a p-type well; an internal n-type region formed under a surface of the p-type well; and a surface p-type region including a highly doped p-type SiGeC epitaxial layer or a polysilicon layer deposited on a top surface of the p-type well over the internal n-type region. The image sensor includes: a photo diode including an internal n-type region and a surface p-type region; a transfer transistor for transmitting photo-charges generated in the photo diode to a floating diffusion node; and a driving transistor for amplifying a variation in an electric potential of the floating diffusion node due to the photo-charges. The image sensor further includes a floating metal layer for functioning as the floating diffusion node and applying an electric potential from a drain of the transfer transistor to a gate of the driving transistor.

High-quality CMOS image sensor and photo diode

Provided are bipolar transistor, BiCMOS device and method of fabricating thereof, in which an existing sub-collector disposed beneath a collector of a SiGe HBT is removed and a collector plug disposed at a lateral side of the collector is approached to a base when fabricating a Si-based very high-speed device, whereby it is possible to fabricate the SiGe HBT and an SOI CMOS on a single substrate, reduce the size of the device and the number of masks to be used, and implement the device of high density, low power consumption, and wideband performance.

Bipolar transistor, BiCMOS device, and method for fabricating thereof

Provided is a low-reference-current generator that includes a circuit employing two feedback loops enabling it to operate even at a low voltage, has a high power supply rejection ratio (PSRR) to control power supply noise, and simply forms a voltage without a voltage-to-current converter used in a conventional general reference current generator. The reference current generator includes: a first voltage generator receiving a predetermined current and generating a first voltage that decreases as temperature increases; a second voltage generator generating a second voltage that increases as temperature increases; a first current generator generating a first current corresponding to the first voltage; a second current generator generating a second current corresponding to the second voltage; and a reference current generator receiving the first current and the second current and generating a reference current that is the sum of the first current and the second current.

Reference current generator

NMOS device formed on SOI substrate and method of fabricating the same

Provided is a voltage-controlled oscillator (VCO) using a current feedback network for use in a wireless communication terminal. The voltage-controlled oscillator has high input impedance and low output impedance, so that a degree of isolation from the external load is excellent, thereby preventing degradation of the Q-factor by the load in overall oscillation circuit. In the voltage-controlled oscillator of the present invention, an LC resonator is provided to generate positive feedback, and negative resistance may be obtained at a wider frequency range by tuning a varactor of the LC resonator. And a boosting inductor is inserted into the positive feedback loop to have a greater negative resistance, therefore it is possible to prevent a problem in which the oscillation does not occur due to the parasitic resistance components generated during circuit fabrication.

Voltage-controlled oscillator using current feedback network

There is provided a feedback amplifier capable of easily controlling its dynamic range without a separate gain control signal generation circuit. The feedback amplifier includes an input terminal detecting an input voltage from input current, a feedback amplification unit amplifying the input voltage to generate an output signal, and an output terminal outputting a signal amplified by the feedback amplification unit. The feedback amplification unit includes a feedback circuit unit including a feedback resistor located between the input terminal and the output terminal, and a feedback transistor connected in parallel to the feedback resistor; and a bias circuit unit supplying a predetermined bias voltage to the feedback transistor of the feedback circuit unit and merged in the feedback amplification unit.

Automatic gain control feedback amplifier

Provided is a method of fabricating a silicon germanium (SiGe) Bi-CMOS device. In the fabrication method, the source and drain of the CMOS device is formed using a silicon germanium (SiGe) heterojunction, instead of silicon, thereby preventing a leakage current resulting from a parasitic bipolar operation. Further, since the source and drain is connected with an external interconnection through the nickel (Ni) silicide layer, the contact resistance is reduced, thereby preventing loss of a necessary voltage for a device operation and accordingly, making it possible to enable a low voltage and low power operation and securing a broad operation region even in a low voltage operation of an analogue circuit.

Method of fabricating SiGe Bi-CMOS device

An optoelectronic device and a method of manufacturing the same which the optoelectronic effect such as light emission or light reception can be increased by forming a dual-structural nano dot to enhance the confinement density of electrons and holes are provided. The optoelectronic device comprises an electron injection layer, a nano dot, and a hole injection layer. The nano dot has a dual structure composed of an external nano dot and an internal dot. The method of manufacturing the optoelectronic device comprises the steps of forming an electron injection layer on a semiconductor substrate; growing nano dot layer on the electron injection layer by an epi-growth method; heating the nano dot layer so that the nano dot has a dual structure composed of an external nano dot and an internal nano dot; and forming a hole injection layer on the overall structure.

Optoelectronic device having dual-structural nano dot and method for manufacturing the same

An X-ray generation system for an ultra fine lithography includes a center electrode having an adjusting member, peripheral electrode having gas flow holes, a metal disc having gas flow holes for generating the X-ray from a plasma, a large capacitor, a transparent cylinder, a discharge member, Be discharge and observing windows, a cylindrical insulator, exhaust holes, a metal container, large electric power spatial gap switches, a current returning wire, an exhaust pump, and gas feeding members. Thereby, the system provides continuous operation and increased stability, controlling and discharging quantity so that the X-ray system can be easily utilized for researching and commercial applications.

Growing community of inventors

Daejeon, South Korea

Jin Yeong Kang