Samsung Electronics Co., Ltd.

Jin-Yeon Won

Jongwon Kim

Tae-wan Lim

Woohyun Park

Keejeong Rho

Jong-Min Lee

Jong-Hyun Park

Joon-Hee Lee

Jin-hyun Shin

Dong-seog Eun

Kee-jeong Rho

Seung-Woo Paek

Joo-Hee Park

Seon-Kyung Kim

Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

Semiconductor memory devices and methods for manufacturing the same

A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that vertical to a top surface of the substrate, a plurality of gate lines and a conductive line on the substrate. The gate lines are stacked on top of each other. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction. The conductive line cuts the gate lines along the first direction. A width of the conductive line is periodically and repeatedly changed.

Vertical memory devices with common source including alternately repeated portions having different widths

According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

Vertical cell-type semiconductor device having protective pattern

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Seoul, South Korea

Jin-Yeon Won