Samsung Electronics Co., Ltd.

Other

Korea Railroad Research Institute

Lee, Jin-wook

Jin-wook Lee

Myeong-Cheol Kim

Kang-Ill Seo

Myong-jong Kwon

Sung-Joon Park

Hong-bae Park

Min-chan Gwak

Jin-Yub Lee

Sang-Won Hwang

Sang-min Lee

Sang-Jin Hyun

Ja-hum Ku

Hyun-Jae Kang

Ki-Hyung Ko

Sung-kee Han

Yong-Min Cho

Min-Gun Park

Ji-ye Kim

Jung-hwan Chun

Bo-un Yoon

Do-hyoung Kim

Sang-Jine Park

In-oh Hwang

Byung-ha Park

Jae-Jik Baek

Dong-Hyun Roh

Kwan-heum Lee

Keun-Hee Bai

Kee-Sang Kwon

Cheol Ham

Young-Ju Park

Seung-mo Ha

Dong-hoon Khang

Ji-Min Jeong

Dae-Young Kwak

Kye-Hyun Baek

Myung-Hoon Jung

Hyung-yong Kim

Myung-gon Kim

Ji-Won Yun

Soo-jin Park

Saim Saher

Chang-yeon Lee

Seung-hoon Kal

Yu-Gyun Shin

Moon-chul Lee

Dong-kyun Kim

Yong-seop Yoon

Chan-Ik Park

Yun-Gi Kim

Wan-don Kim

Tai-Su Park

Yun-Jung Lee

Yun-ho Choi

Young-ung Ha

Hee-Won Lee

Yong-won Jeong

Kang-Deog Suh

Yong-shik Park

Jae-Yeol Song

Dong-Gi Lee

Joon-Suc Jang

Ji-Su Kim

Sang-jin Hyun

Sung-Chul Hong

Kyong-Ae Kim

Heung-sik Park

Suk-Eun Kang

Pyung-moon Zhang

Byoung-Kook Lee

Chang-shin Park

Gyoung-Ho Buh

Sung-young Yun

Hyun-Ho Jung

Sung-Jun Park

Kee-sang Kwon

Dae-young Kwak

Dong-hyun Roh

Hwa-Young Ko

Yeong-Tack Lee

Jee-eun Yang

Donk-sik Shim

Chang-Woo Ryoo

Chan-Ha Kim

Seung-Kyung Ro

Young-Ha Choi

Seong-Hyeok Lee

Sung-woo Myung

An integrated circuit device including a substrate; a fin-type active region protruding from the substrate; a gate line intersecting the fin-type active region and covering a top surface and side walls thereof; a gate insulating capping layer covering the gate line; source/drain regions at sides of the gate line on the fin-type active region; first conductive plugs connected to the source/drain regions; a hard mask layer covering the first conductive plugs; and a second conductive plug between the first conductive plugs, the second conductive plug connected to the gate line by passing through the gate insulating capping layer and having a top surface higher than the top surface of each first conductive plug, wherein the hard mask layer protrudes from the first conductive plugs and toward the second conductive plug so that a portion of the hard mask layer overhangs from an edge of the first conductive plugs.

Method of manufacturing an integrated circuit device including a fin-type active region

An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Method of forming an integrated circuit device having a contact capping layer

Integrated circuit device having fin-type active

Integrated circuit device including an overhanging hard mask layer

A coating film to prevent a conspicuous fingerprint has a water contact angle of no less than 60&#xb0; so that most of water contained in fingerprints on the coating film evaporates without forming a layer adsorbed on the coating film. Further, the coating film has lipophilicity and has a diiodomethane contact angle of no more than 45&#xb0; so that the coating film exhibits enhanced affinity to fingerprints, which primarily contain oily components.

Composition for coating film to prevent conspicuous fingerprints, coating film to prevent conspicuous fingerprints using the composition, and article having the coating film

A semiconductor device is provided. The semiconductor device includes a gate spacer that defines a trench on a substrate and includes an upper part and a lower part, a gate insulating film that extends along sidewalls and a bottom surface of the trench and is not in contact with the upper part of the gate spacer, a lower conductive film that extends on the gate insulating film along the sidewalls and the bottom surface of the trench and is not overlapped with the upper part of the gate spacer, and an upper conductive film on an uppermost part of the gate insulating film on the lower conductive film.

Semiconductor device and method for fabricating the same

A method includes providing a plurality of active regions on a substrate, and at least a first device isolation layer between two of the plurality of active regions, wherein the plurality of active regions extend in a first direction; providing a gate layer extending in a second direction, the gate layer forming a plurality of gate lines including a first gate line and a second gate line extending in a straight line with respect to each other and having a space therebetween, each of the first gate line and second gate line crossing at least one of the active regions, providing an insulation layer covering the first device isolation layer and covering the active region around each of the first and second gate lines; and providing an inter-gate insulation region in the space between the first gate line and the second gate line.

Integrated circuit device and method of manufacturing the same

A semiconductor device includes a substrate, a fin active region pattern on the substrate, the fin active region pattern including an upper region and a lower region, a device isolation layer pattern surrounding the fin active region pattern, a gate pattern on the upper region of the fin active region pattern, and a stressor on the lower region of the fin active region pattern, wherein a top surface of the device isolation layer pattern is lower than a top surface of the upper region and higher than a top surface of the lower region.

Method of manufacturing semiconductor device having stressor

An operating method of a storage device includes a controller: receiving read data from a non-volatile memory; measuring a plurality of threshold voltage distributions respectively corresponding to a plurality of memory units of the non-volatile memory, based on the received read data; measuring a distribution variation between the plurality of memory units, based on the measured plurality of threshold voltage distributions; dynamically determining operation parameters for the non-volatile memory, based on the measured distribution variation; and transmitting, to the non-volatile memory, an operate command, an address, and at least one operation parameter corresponding to the address.

Storage device having parameter calibration function, and operating method thereof

Semiconductor device having stressor and method of manufacturing the same

By supporting a space generated by a settlement of the track bed gravel or asphalt roadbed underneath a concrete rail tie with cylindrical rods, and installing the present invention, one each separately, on the left and right sides of the concrete rail tie, recovery from settlements is automatic, and the response to differential settlements of the left and right rails of the track due to the train load can be easily facilitated, and by installing pressure reducing valves on the upper part of the concrete rail ties, pressure can be reduced while maintaining the track system as is without having to dismantle the concrete rail ties, and accordingly the usability of the concrete rail ties can be improved.

Rail tie having embedded automatic differential settlement compensation apparatus using oil pressure for railroad tracks

In a semiconductor device including a gate line having a relatively narrow width and a relatively smaller pitch and a method of manufacturing the semiconductor device, the semiconductor device includes a substrate having a fin-type active region, a gate insulating layer that covers an upper surface and sides of the fin-type active region, and a gate line that extends and intersects the fin-type active region while covering the upper surface and the both sides of the fin-type active region, the gate line being on the gate insulating layer, wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape.

Finfet semiconductor device and method of manufacturing the same

Growing community of inventors

Seoul, South Korea

Jin-wook Lee