Freescale Semiconductor,inc.

Motorola Corporation

Jin-Wook Jang

Lakshminarayan Viswanathan

Audel Sanchez

Lalgudi M Mahalingam

James Jen-Ho Wang

Russell S Shumway

Alfredo Mendoza

Rajashi Runton

Jason R Fender

Shun Meen Kuo

Vasile Romega Thompson

Terry K Daly

Embodiments of methods for forming a semiconductor device that includes a die and a substrate include pressing together the die and the substrate such that a first gold layer and one or more additional material layers are between the die and the substrate, and performing a bonding operation to form a die attach layer between the die and the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.

Methods for bonding a die and a substrate

Embodiments of a semiconductor device include a primary portion of a substrate, a die, and a die attach layer between the die and the primary portion of the substrate. The die attach layer includes a gold interface layer that includes gold and a plurality of first precipitates in the gold. Each of the first precipitates includes a combination of nickel, cobalt, palladium, gold, and silicon.

Semiconductor devices that include a die bonded to a substrate with a gold interface layer

A method includes providing a silicon-containing die and providing a heat sink having a palladium layer over a first surface of the heat sink. A first gold layer is located over one of a first surface of the die or the palladium layer. The silicon-containing die is bonded to the heat sink, where bonding includes joining the silicon-containing die and the heat sink such that the first gold layer and the palladium layer are between the first surface of the silicon-containing die and the first surface of the heat sink, and heating the first gold layer and the palladium layer to form a die attach layer between the first surface of the silicon-containing die and the first surface of the heat sink, the die attach layer comprising a gold interface layer having a plurality of intermetallic precipitates, each of the plurality of intermetallic precipitates comprising palladium, gold, and silicon.

Die bonding a semiconductor device

A method and device are disclosed in which a a lead-free or low-lead die attach material is applied to a surface. An electronic die is positioned on the die attach material. An oxide of at least a specified thickness is formed over an exposed portion of the die attach material. Wire bonds are formed between the electronic die and the surface, and an encapsulant material is applied over the surface, the oxide, and the electronic die.

Method and apparatus for integrated circuit packages using materials with low melting point

Semiconductor packages () that prevent the leaching of gold from back metal layers () into the solder () and methods for fabricating the same are provided. An exemplary method comprises providing a semiconductor wafer stack () including metal pads () and a substrate (). An adhesion/plating layer () is formed on the substrate (). A layer of gold () is plated on the adhesion/plating layer (). The layer of gold is etched in a street area () to expose edge portions () of the layer of gold () and the adhesion/plating layer (). A layer of barrier metal () is deposited to form an edge seal () about the exposed edge portions (). The edge seal () prevents the leaching of gold from back metal layers () into the solder () when the wafer stack () is soldered to a leadframe ().

Semiconductor package and method for forming the same

A semiconductor device () is provided. The device () comprises a die () having a contact pad () thereon, a redistribution conductor () having a base portion () which is in electrical communication with the contact pad () and a laterally extending portion (), a bumped contact () which is in electrical communication with the redistribution conductor (), and a passivation layer () disposed between the laterally extending portion () of the redistribution conductor () and the die (). Preferably, the redistribution conductor () is convoluted and is adapted to peel or delaminate from the passivation layer () under sufficient stress so that it can shift relative to the passivation layer () and base portion () to relieve mechanical stress between substrate () and the die (). Bump and coiled redistribution conductor () accommodating small CTE mis-match strain without failure allows DCA flip-chip to be reliable without underfill or additional assembly process.

Semiconductor device with strain relieving bump design

A semiconductor device ( ) is provided. The device ( ) comprises a die ( ) having a contact pad ( ) thereon, a redistribution conductor ( ) having a base portion ( ) which is in electrical communication with the contact pad ( ) and a laterally extending portion ( ), a bumped contact ( ) which is in electrical communication with the redistribution conductor ( ), and a passivation layer ( ) disposed between the laterally extending portion ( ) of the redistribution conductor ( ) and the die ( ). Preferably, the redistribution conductor ( ) is convoluted and is adapted to peel or delaminate from the passivation layer ( ) under sufficient stress so that it can shift relative to the passivation layer ( ) and base portion ( ) to relieve mechanical stress between substrate ( ) and the die ( ). Bump and coiled redistribution conductor ( ) accommodating small CTE mis-match strain without failure allows DCA flip-chip to be reliable without underfill or additional assembly process.

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Chandler, AZ, United States of America

Jin-Wook Jang