Samsung Electronics Co., Ltd.

Samsung Medison Co., Ltd.

Daegu Gyeongbuk Institute of Science and Technology

Dorco Co., Ltd.

Cj Healthcare Corporation

Lmca Co., Ltd.

Medison Co., Ltd.

Hk Inno.n Corporation

Jin Woo Jung

Jae Bong Chun

Dong Ryul Shin

Se Hyun Park

Jae Yk Kim

Min Sakong

Gyu Sub Kim

Chae Up Yoo

Ho Saeng Kim

In Young Lee

Yoon Jae Lee

Hyun Suk Choi

Jinin So

Tae Young Kim

Hyun Jun Jung

Kyungsoo Kim

Woo Suk Kang

Gil Ju Jin

Se Woong Kim

Joon Ho Byun

Young Jun Cho

Dong Min Shin

Daehoon Kim

Su Min Yun

Sung Gi Kim

Yeon Woo Kim

Seong Tae Jeong

So Young Lee

Yong Uk Shin

Jae Ho Lee

Won Hee Lee

Dong Hyun Kim

Dong Jin Lee

Jae Joon Lee

Kyung Min Lee

Sangjun Park

Minho Kim

Sung Soo Jung

Ji Su Kim

Jin Hwan Park

Jae Hoo Park

Sang Hak Kim

Sung Hee Son

Sang Ki Yoon

Ju Hyun Lee

Kwang Sung Hwang

Jeong Roh Lee

Jong-Geon Lee

Dong Hyun Ko

Byoung Uk Yoon

Gyu Sung Do

Jae Hoon Jo

Je Hun Jong

Young Gwon Koo

Ui Chul Jeong

Byung Chan Jang

Yongsuk Kwon

Jonggeon Lee

Jeong Ho Ahn

Jeonghyeon Cho

Ahmed Hussain

Igor Shcherbatko

Kuo Cheng Chen

Jae Kwang Sim

Hae Yeon Kim

Soon Ho Hwang

Woo Young Kan

Sung Koo Park

In Seong Song

Dae Sung Ko

Huu Lam Vuong Nguyen

Song Hyeon Kim

Jeong Cheol Seo

Se Ki Jang

Jung Hoon Seo

Kyung Gu Kim

Yong Soo Kwak

Kyung Il Seo

Chan Kyu An

Tae Hwan Wi

Yong Sub Jung

Jin In So

Jong-Sun Ko

Da Jeong Kim

Yong Jae Kim

Myung Hun Jeong

Yoon Ah Kim

So Young Ki

Keunho Lee

Wookjin Lee

Won-Hyuk Jung

Kwangsung Hwang

Yoonah Kim

Nguyen Huu Lam Vuong

Bo Ra Kim

Jung-Kil Kang

Chi Hye Park

Memory systems and methods for operating the same. A memory system comprises a first memory, a second memory having an operating speed different from that of the first memory, a storage unit configured to store an instruction, a prefetcher configured to update prefetcher data in response to occurrence of cache hits and a processor configured to execute the instruction stored in the storage unit. When the instruction is executed, the processor is configured to generate prefetcher friendly data by filtering the prefetcher data, set a prefetcher friendly bit in a first pointer area corresponding to the first memory and a second pointer area corresponding to the second memory based on the prefetcher friendly data, and determine whether data of the first pointer area and the second pointer area are migrated, in consideration of a reference bit and the prefetcher friendly bit of the first and second pointer areas.

Memory systems and methods for operating memory systems

A processor includes a processing core configured to process each of a plurality of requests by accessing a corresponding one of a first memory and a second memory, a latency monitor configured to generate first latency information and second latency information, the first latency information comprising a first access latency to the first memory, and the second latency information comprising a second access latency to the second memory, a plurality of cache ways divided into a first partition and a second partition, and a decision engine configured to allocate each of the plurality of cache ways to one of the first partition and the second partition, based on the first latency information and the second latency information.

Processor, system, and method for dynamic cache allocation

A display apparatus includes a frame, a display panel configured to be detachable from the frame, and a position adjustment device provided between the frame and the display panel. The position adjustment device includes a first position adjusting member configured to adjust a position of the display panel in a first direction moving vertically with respect to the frame, and a second position adjusting member configured to adjust the position of the display panel in a second direction moving horizontally with respect to the frame.

Display apparatus

A wearable device which is mountable on a wrist of a user includes a housing including a metal structure, a display positioned within the housing, wherein the display includes a metal layer positioned within the metal structure and spaced apart from the metal structure by a given gap, a printed circuit board (PCB) positioned within the housing and including a ground region, and a control circuit positioned on the PCB and configured to feed a first point of the metal structure. The metal layer is electrically connected with the ground region of the PCB at a second point spaced from the first point by a given angle.

Antenna for wearable device

Disclosed is an electronic device that includes a display that outputs display data, an antenna arranged on a display area of the display, at least one processor electrically connected to the display, and a memory electrically connected to the processor, where the memory stores instructions that, when executed, cause the processor to correct the display data based on characteristic information of the antenna when a display location of the display data overlaps an arranged location of the antenna when the instructions are executed. In addition, various embodiments that are understood through the present disclosure are possible.

Screen display method and electronic device supporting same

A booting method of a computing system, which includes a memory module including a processing device connected to a plurality of memory devices, including: powering up the computing system; after powering up the computing system, performing first memory training on the plurality of memory devices by the processing device in the memory module, and generating a module ready signal indicating completion of the first memory training; after powering up the computing system, performing a first booting sequence by a host device, the host device executing basic input/output system (BIOS) code of a BIOS memory included in the computing system; waiting for the module ready signal to be received from the memory module in the host device after performing the first booting sequence; and receiving the module ready signal in the host device, and performing a second booting sequence based on the module ready signal.

Booting method of computing system including memory module with processing device mounted

A communication method performed in an electronic device including a conductive pattern and the electronic device are provided. The electronic device includes a conductive pattern used as a radiator for wireless communication, a feeding unit connected with the conductive pattern, a ground unit connected with the conductive pattern, a first impedance matching circuit disposed in a first area adjacent to the feeding unit and connected to the conductive pattern, a second impedance matching circuit disposed in a second area adjacent to the conductive pattern and connected to the conductive pattern, and a control unit that matches impedance by controlling at least one of the first impedance matching circuit and the second impedance matching circuit by a closed-loop scheme.

Antenna for wireless communication and electronic device including the same

An ultrasonic includes: a piezoelectric layer; an absorbing layer disposed at a lower portion of the piezoelectric layer, configured to absorb an acoustic signal; and a connection part disposed between the piezoelectric layer and the absorbing layer. The connection part may deform at least partially so that a plurality of acoustic signals radiated from the piezoelectric layer due to the connection part have different magnitudes. In the case of the ultrasonic probe, since the magnitude of the acoustic energy radiated from the center of the ultrasonic probe is larger than the magnitude of the acoustic energy radiated from the side of the ultrasonic probe, the directivity of the ultrasonic signal is improved and a side lobe is decreased. In addition, an apodization effect capable of suppressing overlapping between adjacent phases can be obtained by using a difference in the magnitude of the acoustic energy to be radiated.

Ultrasonic probe

Memory modules and memory systems having the same are provided. A memory module may include command/address terminals, data terminals, at least one monitoring terminal, a buffer, and a plurality of semiconductor memory devices. The buffer may be configured to receive and buffer data applied through the data terminals and a command/address applied through the command/address terminals to generate buffered write data and a buffered command/address. The buffer may be configured to buffer the buffered write data and the buffered command/address to generate module data and a module command/address, and store and then transmit at least one portion of the buffered write data as monitoring data through the at least one monitoring terminal. The plurality of semiconductor memory devices may be configured to receive and store the module data in response to the module command/address.

Memory modules and memory systems having the same

A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

Memory modules and methods of operating same

An electronic device includes a housing that includes a first plate, a second plate facing a direction opposite the first plate, and a side member surrounding a space between the first plate and the second plate, an antenna structure that includes a plurality of dielectric layers perpendicular to the side member and parallel to the first plate, a first array of conductive plates aligned in a first direction perpendicular to the first plate at a first dielectric layer of the dielectric layers, a second array of conductive plates spaced from the first array and aligned in the first direction at the first dielectric layer, wherein the second array is farther from the first plate than the first array, at least one ground plane positioned on at least one of the dielectric layers and interposed between the first array and the second array, when viewed from above the side member, and a wireless communication circuit electrically connected to the first array and the second array and configured to transmit and/or receive a signal having a frequency in a range of 20 GHz to 100 GHz.

Antenna structure and electronic device comprising antenna structure

The present disclosure relates to a pharmaceutical composition for preventing or treating non-alcoholic fatty liver disease or dyslipidemia comprising an aminoalkylbenzothiazepine derivative or a pharmaceutically acceptable salt thereof as an active ingredient.

Use of aminoalkylbenzothiazepine derivatives

An antenna device is provided and includes a plurality of antenna radiators arranged in an array, a ground member in operable communication with the plurality of antenna radiators, a plurality of conductive cells arranged on the plurality of antenna radiators, and a plurality of feeding lines electrically connected to the plurality of antenna radiators.

Electronic device comprising array antenna

Growing community of inventors

Seoul, South Korea

Jin Woo Jung