Sambanova Systems, Inc.

Oracle International Corporation

Sun Microsystems, Inc.

Oracle America, Inc.

Jin-uk Shin

Fahim Ur Rahman

Mahmood Khayatzadeh

Zuxu Qin

Dennis L Wendell

Howard L Levy

Ha Pham

Sang-Min Lee

Lancelot Y Kwong

Gaurav Shrivastav

Effendy Kumala

Vaibhav Gupta

A clock stretcher includes a delay line, a control unit, and a combiner. The delay line outputs a series of delayed phases of an input clock. The control circuit is clocked by the input clock. It outputs a series of delayed phase enable signals. The combiner circuit receives the delayed phases from the delay line and the delayed phase enable signals from the control circuit, and outputs a modified clock. The control circuit determines if stretching has started, if wraparound must occur, and if a next phase must be enabled. The combiner retimes a delayed phase enable signal for a first delayed phase using a flipflop clocked by a second delayed phase to generate a retimed phase enable signal. The combiner uses the retimed phase enable signal to pass a pulse of the first delayed phase to the output as a pulse of the modified clock.

Variable-length clock stretcher with combiner timing logic

A clock stretcher includes a DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The DLL has a phase error because of its finite bandwidth. The clock stretcher measures the phase error and corrects for a glitch in the modified clock signal by using the phase error when phase selection wraparound occurs. The clock stretcher may operate from a power supply that has droops, without intervening voltage regulation.

Variable-length clock stretcher with correction for glitches due to finite DLL bandwidth

A clock stretcher includes a digital DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. The digital DLL corrects its delay speed at discrete times, during which it may be active. If the DLL delay line becomes slower while it is active, the modified clock signal would incur a glitch. The clock stretcher corrects for this glitch by using an increased hop code when a speed change occurs. The clock stretcher may operate from a sensed power supply without intervening voltage regulation.

Variable-length clock stretcher with correction for digital DLL glitches

A clock stretcher includes a DLL that derives delayed versions of an input clock signal. The clock stretcher has passive and stretching modes. It operates from a sensed power supply without intervening voltage regulation. In passive mode, it forwards input clock pulses to the clock stretcher output. The input clock pulses are delayed by fewer than 10 DLL delay line delay stages. In stretching mode, a combiner cyclically selects the delayed versions of the input clock signal to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. To enter passive mode, the clock stretcher tests if a passive mode entry threshold is met. The threshold includes two conditions: the hop code must be zero, and phase selection must have reached a wraparound point that may have been corrected for a delay line offset.

Variable-length clock stretcher with passive mode jitter reduction

A clock stretcher includes a DLL that derives delayed versions of an input clock signal, and a combiner that cyclically selects the delayed versions to generate a modified clock signal. The combiner uses a hop code, dependent on a sensed condition, to determine the step size for the cyclical selection. The DLL may have a phase error that would cause a glitch in the modified clock during phase selection wraparound. The clock stretcher proactively increases the step size during wraparound by adding an offset skip parameter value to the hop code. The clock stretcher may operate from a sensed power supply without intervening voltage regulation.

Variable-length clock stretcher with correction for glitches due to phase detector offset

A process-tolerant large-swing sense amplifier with latching capability includes top-array and bottom-array access. The sense amplifier provides improved tolerance to process variation, reduces design complexity, reduces power consumption, and reduces the physical footprint of the circuit. In addition, the sense amplifier provides write-through functionality through the read data bus.

Process tolerant large-swing sense amplfier with latching capability

A static complementary transistor type logic gate circuit includes a plurality of input terminals for receiving a corresponding plurality of input signals, and an output terminal. The logic gate circuit further includes a first plurality of transistors of one conductivity type, arranged to form a plurality of pullup paths for selectively connecting the output terminal, through one or more intermediate nodes, to a positive supply voltage based on the plurality of input signals; and a second plurality of transistors of the complementary conductivity type, arranged to form a plurality of pulldown paths for selectively connecting the output terminal, through one or more intermediate nodes, to a negative supply voltage based on the plurality of input signals. A precharge device is configured to selectively charge an intermediate node to the far-side supply voltage when the intermediate node is disconnected from the near-side supply voltage and disconnected from the output terminal.

High-speed static XOR circuit

A hardware implemented method for accessing data in a multicycle operations cache is provided. In this hardware implemented method, a request to access the data in a sub-bank of the multicycle operations cache is received. If the sub-bank is accessed in a previous, consecutive clock cycle, then the request to access the data in the sub-bank is ignored. Else, if the sub-bank is not accessed in the previous, consecutive clock cycle, then the data is allowed to be accessed in the sub-bank. A memory chip and a system for accessing data in the multicycle operations cache also are described.

System and method for accessing data in a multicycle operations cache

A Negative Bias Temperature Instability (NBTI) tolerant sense amplifier is provided. The sense amplifier includes an input stage having a pair of balanced isolation devices. Each of the balanced isolation devices has an input connected to receive a separate one of a pair of differential input signals. Each of the balanced isolation devices also has a gate that is connected to receive a common bias voltage. The sense amplifier further includes a sense stage connected to the input stage. The sense stage is configured to receive and amplify a higher signal to be provided by the pair of balanced isolation devices. The sense amplifier is also equipped to operate a low voltage levels.

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San Jose, CA, United States of America

Jin-uk Shin