Fujitsu Corporation

Jin Takahashi

Hiroshi Nakayama

Seishi Okada

Toshikazu Ueki

Makoto Hataida

Fumitake Sugano

Shinya Kato

Takayoshi Kyono

Norihiko Fukuzumi

Ryuichi Nisiyama

It is provided an information processing system. A first processing unit instructs a second processing unit to update the state management information regarding first data managed by the second processing unit when the first processing unit accesses the first data and detects an error regarding the first data, the second processing unit issues a command for discarding the first data acquired by a processing unit other than the second processing unit to the processing unit other than the second processing unit, when the processing unit which acquires the first data receives the command, the processing unit which acquires the first data discards the first data and transmits a result of the discarding of the first data to the second processing unit, and the second processing unit updates the state management information regarding the first data based on the result received from the processing unit which acquires the first data.

Information processing system, information processing method and information processing apparatus

A node includes: an arithmetic processing device; and a first memory, wherein the arithmetic processing device includes: a processor core; a storing circuit to store a first failure node list in which first information indicating that a failure has occurred or second information indicating that no failure has occurred is set for each of nodes; a request issuing circuit to issue a first request to a second memory provided at a first node among the nodes; a setting circuit to set the first information for the first node in the first failure node list when the first request has timed out; and an issuance inhibition circuit to inhibit, based on a second request to the second memory from the processor core, the second request from being issued by the request issuing circuit when the first information is set for the first node in the first failure node list.

Node, arithmetic processing device, and arithmetic processing method

According to an aspect of the embodiment, a system control apparatus includes a control signal transmitting unit which transmits a control signal to control circuits via first signal line. The control signal includes a command for performing a control setting on other control circuits other than own control circuit or to all control circuits. Each control circuit includes a signal receiving unit which receives the control signal transmitted from the control signal transmitting unit via the first signal line, a signal transfer unit which transfers the command included in the received control signal via second signal lines to the control circuit, and a control setting unit which performs the control setting on the own control circuit according to the command included in the received control signal or a command transferred from the other control circuits other than the own control circuit.

Information processing apparatus and method for controlling information processing apparatus

The method for reconfiguring an information processing apparatus includes: transmitting, by the system management unit, a register setting request to set a register included in the control unit to a predetermined value to all of the system boards within the information processing apparatus, when a system board is added to or removed from any of the partitions; setting, by the system board that receives the register setting request, a register of a control unit of the local system board to the predetermined value, if a partition to which the local system board belongs includes the system board to be added or removed; and ignoring, by the system board that receives the register setting request, the register setting request if the partition to which the local system board belongs does not include the system board to be added or removed.

Information processing apparatus and method for reconfiguring the information processing apparatus

An error notification method notifies errors generated in first and second processor systems to each processor within the first and second processor systems, in a computer system that includes the first processor system operable in a normal mode and the second processor system operable together with the first processor system in a mirror mode. The error notification method generates an error interrupt signal that indicates each error by a corresponding one of a plurality of error levels, reduces the error level of a corresponding error interrupt signal when the error within the first processor system is avoided in the mirror mode, and notifies the error to each processor within the first and second processor systems using the error interrupt signal.

Error notification method and information processing apparatus

An information processing apparatus includes a plurality of computing units. At least one of the computing units includes a recording unit that records a status of an error occurrence in each of the computing units. The each of the computing units includes an error notifying unit that notifies the error occurrence to at least one of the computing units that includes the recording unit when an error occurs in the each of the computing units itself.

Information processing apparatus and error detecting method

A data transmitter and a data receiver generate respective synchronous signals from a common reference signal. The data receiver adjusts a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of received parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal, and loads each one-bit data signal into a data buffer in accordance with the adjusted clock signal. Then, the data receiver reads the data held in the data buffer, in accordance with a second clock signal and in synchronization with the receiver synchronous signal. A memory position where the data signal is to be loaded is initialized when a training pattern transmitted in synchronization with the transmitter synchronous signal is detected.

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Kawasaki, Japan

Jin Takahashi